Quadrature Encoder to up/down pulses with discrete logic - paging logic gate gurus

[Spehro Pefhany]

Hi all,

A hobbyist has asked for help using a mechanical encoder in the
following circuit:

http://pages.interlog.com/~speff/usefulinfo/dec_circuit.pdf

Looks like he's generating up/down pulses to simulate keyboard presses
(using the analog switches) from the quadrature outputs.

The problem is that circuit (he says) works fine with this kind of
encoder:

Loading Image...

Which has guaranteed high B signal (high means that the mechanical
switch is "closed" in this case) at the detent.

He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf

Where the B signal can be either high or low at the detent, and may
actually change if the switch is teased.

Normally I'd do this with a microcontroller by sampling the two
signals at a few hundred Hz and monitoring state transitions (legal
and illegal) after debouncing (looking for states stable for a couple
of samples). This works very well and is reliable. I've also done it
by locking out additional changes by latching a bit. Either way works
fine, in C, 8051 ASM or PIC ASM.

Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?

Best regards,
Spehro Pefhany

[Frank Bemelman]

Post by Spehro Pefhany
Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?

I don't see a quick fix, other than getting rid of the 3 logic IC's
and replacing them with an 8 pin PIC like a 12F628 or something.

Of course you can mess around with differentiators to translate
the edges in short pulses, set/reset flipflops, but I wouldn't
recommend that. After all, the first circuit wasn't perfect either,
even if it may have worked reasonably well.

[ACIT]

Now I see Spehro has no clue either...

Post by Frank Bemelman

Post by Spehro Pefhany
Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?

I don't see a quick fix, other than getting rid of the 3 logic IC's
and replacing them with an 8 pin PIC like a 12F628 or something.
Of course you can mess around with differentiators to translate
the edges in short pulses, set/reset flipflops, but I wouldn't
recommend that. After all, the first circuit wasn't perfect either,
even if it may have worked reasonably well.
--
Thanks, Frank.
(remove 'x' and 'invalid' when replying by email)

[Spehro Pefhany]

On Wed, 21 Apr 2004 11:55:28 -0400, the renowned "ACIT"

Post by ACIT
Now I see Spehro has no clue either...

Plenty of clues, kid, just swamped with, and immersed in, well paying
EE work.

How 'bout them Sens? ;-)

Best regards,
Spehro Pefhany

[ACIT]

it's a small world Spehro. Small enough for us to have a common customer
:0

Best Regards

Post by Spehro Pefhany
On Wed, 21 Apr 2004 11:55:28 -0400, the renowned "ACIT"

Post by ACIT
Now I see Spehro has no clue either...

Plenty of clues, kid, just swamped with, and immersed in, well paying
EE work.
How 'bout them Sens? ;-)
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"

http://www.trexon.com
http://www.speff.com

[Spehro Pefhany]

On Wed, 21 Apr 2004 14:23:41 -0400, the renowned "ACIT"

Post by ACIT
it's a small world Spehro. Small enough for us to have a common customer
:0

Do tell...

Best regards,
Spehro Pefhany

[j.b. miller]

How about a trip to www.lsicsi.com and look at the datasheets,app. notes,
etc.

I used their encoders for years as they are far superior to the HP units.

Their encoders , ls7166 etc were always rock stable, which is kinda
important in helicopters :)

just another path.....down the road to knowledge

Jay Miller
Temtronic Designs Inc.

[R Adsett]

Post by Spehro Pefhany
Hi all,
A hobbyist has asked for help using a mechanical encoder in the
http://pages.interlog.com/~speff/usefulinfo/dec_circuit.pdf
Looks like he's generating up/down pulses to simulate keyboard presses
(using the analog switches) from the quadrature outputs.
The problem is that circuit (he says) works fine with this kind of
http://pages.interlog.com/~speff/usefulinfo/Rotary_Config.jpg
Which has guaranteed high B signal (high means that the mechanical
switch is "closed" in this case) at the detent.
He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf
Where the B signal can be either high or low at the detent, and may
actually change if the switch is teased.
Normally I'd do this with a microcontroller by sampling the two
signals at a few hundred Hz and monitoring state transitions (legal
and illegal) after debouncing (looking for states stable for a couple
of samples). This works very well and is reliable. I've also done it
by locking out additional changes by latching a bit. Either way works
fine, in C, 8051 ASM or PIC ASM.
Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?
Best regards,
Spehro Pefhany

How about an A clock B/B clock A circuit? The two channels are fed
through a circuit such that the B output is clocked on the edges of the A
input and the A output is clocked on the edges of the B input. If either
one is sitting on an edge the only effect is to repeatedly clock in the
other channel which should be at a DC level. The downside is that you
can (will? it's been a while) lose an edge when changing directions. I
first ran across it in an Intel appnote. You can generate a suitable
clock by xoring the channels together. That will give you a positive
going clock on the edges of one channel and its inverse will give you the
edges for the other channel.

Robert

[R Adsett]

Post by R Adsett
How about an A clock B/B clock A circuit? The two channels are fed
through a circuit such that the B output is clocked on the edges of the A
input and the A output is clocked on the edges of the B input. If either
one is sitting on an edge the only effect is to repeatedly clock in the
other channel which should be at a DC level. The downside is that you
can (will? it's been a while) lose an edge when changing directions. I
first ran across it in an Intel appnote. You can generate a suitable
clock by xoring the channels together. That will give you a positive
going clock on the edges of one channel and its inverse will give you the
edges for the other channel.

So much for memory. The A clock B works but the xor to get the clock
only works in one direction, in the other direction you end up clocking
edges ( you want the inverse clock). Perhaps someone has a clever
approach for clocking on both edges of the signal?

Robert

[Spehro Pefhany]

On Wed, 21 Apr 2004 16:19:47 GMT, the renowned R Adsett

Post by R Adsett
How about an A clock B/B clock A circuit? The two channels are fed
through a circuit such that the B output is clocked on the edges of the A
input and the A output is clocked on the edges of the B input. If either
one is sitting on an edge the only effect is to repeatedly clock in the
other channel which should be at a DC level. The downside is that you
can (will? it's been a while) lose an edge when changing directions. I
first ran across it in an Intel appnote. You can generate a suitable
clock by xoring the channels together. That will give you a positive
going clock on the edges of one channel and its inverse will give you the
edges for the other channel.
Robert

Hmm.. not exactly a simple mod of the orginal circuit, but I came up
with this over lunch. Modulo input polarity, I think it will work
pretty well and it's the same number of chips total (four for 2
encoders).



Vdd or Gnd 1/4 HC08
| __ .----.
.-. .-------------------------| | | A|-
4.7K| | | |& |--|C |
| | 1/4 ' 1/4 1/2 x--|__| | B|-
'-' 33K HC132 | HC132 HC74 | '----'
A | ___ __ | __ .------. | 1/4 HC4066
----x-|___|----x--| | x---| | | Q |--'
| | |& |o---x |& |o----|CP |
0.1uF --- '--|__| x---|__| | |
--- | ---|D /Q |--.
| | | '------' |
| | | |
Vdd or Gnd === | | | 1/4 HC08
| GND | | | __ .----.
.-. | | x--| | | A|-
4.7K | | | ' |& |--|C |
| | '-------------------------|__| | B|-
'-' 33K . '----'
B | ___ | 1/4 HC4066
---x-|___|--------------------------'
|
---
0.01uF ---
|
|
===
GND


There may be a way to reduce it using JK FFs rather than D type, but
that would probably give me a headache.

Best regards,
Spehro Pefhany

[GPG]

I have used this
http://homepages.slingshot.co.nz/~peg/
to interface with

http://www.xkeys.com/custom/xkmatrix.php
For a mate's homebuilt flight simulator cockpit

[Fred Bloggs]

Post by GPG
I have used this
http://homepages.slingshot.co.nz/~peg/
to interface with

Clever- the same can be done with an HC neg edge triggered FF, but
remember, the main pitfall here is that the encoder does not guarantee
the B channel state at the detent- so your FF may not be RESET and the
output remains stuck high.

[GPG]

Post by Fred Bloggs

Post by GPG
I have used this
http://homepages.slingshot.co.nz/~peg/
to interface with

Clever- the same can be done with an HC neg edge triggered FF, but
remember, the main pitfall here is that the encoder does not guarantee
the B channel state at the detent- so your FF may not be RESET and the
output remains stuck high.

The board does not care. It can be set so that a positive or a negative
or both edges result in a keypush

[Fred Bloggs]

Post by GPG

Post by Fred Bloggs

Post by GPG
I have used this
http://homepages.slingshot.co.nz/~peg/
to interface with

Clever- the same can be done with an HC neg edge triggered FF, but
remember, the main pitfall here is that the encoder does not guarantee
the B channel state at the detent- so your FF may not be RESET and the
output remains stuck high.

The board does not care. It can be set so that a positive or a negative
or both edges result in a keypush

Your idea is flawed in the context of the subject encoder-

[GPG]

Post by GPG

Post by Fred Bloggs
Clever- the same can be done with an HC neg edge triggered FF, but
remember, the main pitfall here is that the encoder does not guarantee
the B channel state at the detent- so your FF may not be RESET and the
output remains stuck high.

The board does not care. It can be set so that a positive or a negative
or both edges result in a keypush

Your idea is flawed in the context of the subject encoder-????????

If you are using it with a conventional pc keyboard, turn off repeat,
the reset will occur when the input changes F or Rev.

[petrus bitbyter]

Post by Spehro Pefhany
Hi all,
A hobbyist has asked for help using a mechanical encoder in the
http://pages.interlog.com/~speff/usefulinfo/dec_circuit.pdf
Looks like he's generating up/down pulses to simulate keyboard presses
(using the analog switches) from the quadrature outputs.
The problem is that circuit (he says) works fine with this kind of
http://pages.interlog.com/~speff/usefulinfo/Rotary_Config.jpg
Which has guaranteed high B signal (high means that the mechanical
switch is "closed" in this case) at the detent.
He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf
Where the B signal can be either high or low at the detent, and may
actually change if the switch is teased.
Normally I'd do this with a microcontroller by sampling the two
signals at a few hundred Hz and monitoring state transitions (legal
and illegal) after debouncing (looking for states stable for a couple
of samples). This works very well and is reliable. I've also done it
by locking out additional changes by latching a bit. Either way works
fine, in C, 8051 ASM or PIC ASM.
Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"

http://www.trexon.com
http://www.speff.com


Spehro,

Looking at the electronics I'd say they "only" do debouncing, turning the
bouncing mechanical switches into clean electronic ones. I believe it will
work allright with the far east (may be far west for you) rotary switch.
Your Trexon however is fundamental unstable on its detent. A babies breath -
so to say - may make the B signal bounce like hell and you cannot know
what's going on until the A-signal changes. Even a long time unchanging B
means nothing. Maybe the baby turned his head. No need to say logic does not
like it although the switch can be used with micros in which the problem
relatively easy can be handled in software.

The only solution I can think about at this time of the night is adding some
dirty logic to the outputs of the debounce circuits. When A is ON and B
changes nothing has to be done, but when A is OFF and B changes ignore it
until A changes. Then change B if you need to and delay the changing of A
for an appropriate time.

petrus


---
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[EEng]

On Wed, 21 Apr 2004 12:00:25 GMT, Spehro Pefhany

Post by Spehro Pefhany
Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?
Best regards,
Spehro Pefhany

Sphero,

Do I understand he wants output at both high and low detente, or just
high? Either way:

Given the inputs, what outputs are desired?

Ain Bin :A1 B1 A2 B2
0 0 : detente?
0 1 :
1 0 :
1 1 : detente?

Karnaugh map it and do it with gates.

EEng

[Winfield Hill]

Spehro Pefhany wrote...

Post by Spehro Pefhany
He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf

Does your 18-pulses per revolution spec mean 18 cycles of one
signal channel, e.g., "signal A" and does it mean 18 detents
per rev? If so, a detect coincident with Signal B is fine for
an 18-step/rev application. One should only seek one digital
step per detent anyway. And the detent is best placed midway
between the digital step transitions, just like your encoder.

Thanks,
- Win

whill_at_picovolt-dot-com (use hill_at_rowland-dot-org for now)

[Spehro Pefhany]

On 21 Apr 2004 18:50:50 -0700, the renowned Winfield Hill

Post by Winfield Hill
Spehro Pefhany wrote...

Post by Spehro Pefhany
He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf

Does your 18-pulses per revolution spec mean 18 cycles of one
signal channel, e.g., "signal A" and does it mean 18 detents
per rev? If so, a detect coincident with Signal B is fine for
an 18-step/rev application. One should only seek one digital
step per detent anyway. And the detent is best placed midway
between the digital step transitions, just like your encoder.

Hi, Win:-

There are 18 total cycles (A plus B transitions)- so four edges per
detent, so it works out just fine. That's the way that all the
detented mechanical encoders that I've seen work.

There may be some confusion because sometimes people try with motor
quadrature encoders (optical) to increase the resolution by using more
edges, but that's not what you want with this kind of thing. You want
each detent to be one increment up or down.

Best regards,
Spehro Pefhany

[Rich Grise]

Post by Spehro Pefhany
On 21 Apr 2004 18:50:50 -0700, the renowned Winfield Hill

Post by Winfield Hill
Spehro Pefhany wrote...

Post by Spehro Pefhany
He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf

Does your 18-pulses per revolution spec mean 18 cycles of one
signal channel, e.g., "signal A" and does it mean 18 detents
per rev? If so, a detect coincident with Signal B is fine for
an 18-step/rev application. One should only seek one digital
step per detent anyway. And the detent is best placed midway
between the digital step transitions, just like your encoder.

Hi, Win:-
There are 18 total cycles (A plus B transitions)- so four edges per
detent, so it works out just fine. That's the way that all the
detented mechanical encoders that I've seen work.
There may be some confusion because sometimes people try with motor
quadrature encoders (optical) to increase the resolution by using more
edges, but that's not what you want with this kind of thing. You want
each detent to be one increment up or down.

Well, when you're at the detent, B is indeterminate. But A is high.
So, when A is high, ignore B.

When A is low, a low-to-high on B means "one click clockwise", and
a high-to-low on B means "one click counter-clockwise". What's so
hard about that?

Cheers!
Rich

[Spehro Pefhany]

On Fri, 23 Apr 2004 17:08:06 GMT, the renowned "Rich Grise"

Post by Rich Grise
Well, when you're at the detent, B is indeterminate. But A is high.
So, when A is high, ignore B.
When A is low, a low-to-high on B means "one click clockwise", and
a high-to-low on B means "one click counter-clockwise". What's so
hard about that?

Debouncing and optimizing the logic into a minimum number of easily
available packages. It's also a bite-sized amusing problem that a few
people here can solve with their eyes closed.

Best regards,
Spehro Pefhany

[Fred Bloggs]

Post by Spehro Pefhany
Hi all,
A hobbyist has asked for help using a mechanical encoder in the
http://pages.interlog.com/~speff/usefulinfo/dec_circuit.pdf
Looks like he's generating up/down pulses to simulate keyboard presses
(using the analog switches) from the quadrature outputs.
The problem is that circuit (he says) works fine with this kind of
http://pages.interlog.com/~speff/usefulinfo/Rotary_Config.jpg
Which has guaranteed high B signal (high means that the mechanical
switch is "closed" in this case) at the detent.
He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf
Where the B signal can be either high or low at the detent, and may
actually change if the switch is teased.
Normally I'd do this with a microcontroller by sampling the two
signals at a few hundred Hz and monitoring state transitions (legal
and illegal) after debouncing (looking for states stable for a couple
of samples). This works very well and is reliable. I've also done it
by locking out additional changes by latching a bit. Either way works
fine, in C, 8051 ASM or PIC ASM.
Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?
Best regards,
Spehro Pefhany

I am not sure if this right-but if you say "simulated key press" then to
me that means only one switch on each channel changes state depending on
rotation direction:

Please view in a fixed-width font such as Courier.

.
.
. DETENT DETENT DETENT DETENT
. | | | |
. | | | |
. | | | | | |
. +--|---+ +--|---+ +------+ +------+
. CH A | | | | | | | | | | | |
. | | | | | | | | | | | |
. -+ | +------+ | +------+ | +------+ | +------
. | | | | | |
. +------+ +---|--+ | +------+ +------
. CH B | | | | | | | | |
. | | | | | | | | |
. ----+ +------+ | +---|--+ +------+
. | | | | | |
. | |
. OFF | |
. +- | |
. | | |
. ON | | |
. -----+ | |
. | |
. | |
. >---CW--> | |
. | |
. | | | | | |
. OFF -|---+ +------+---+ +---|------+ +----------
. | | | | | | | | | | |
. SWA | | | | | | | | | | |
. ON | +--+ | +--+ | | +--+ |
. | | | | |
. OFF --------------------------|-----------------------
. | | | | |
. SWB | | | | |
. | | | | |
. | | | | |
. |
. |
. <--CCW--< |
. |
. |
. | | | | |
. OFF --------------------------|-----------------------
. | | | | |
. SWA | | | | |
. | | | | |
. | | | | |
. | | | | |
. +----------+ +----------+ +----------+ +-----
. | | | | | | |
. | | | | | | |
. --+ +--+ +--+ +--+
. | | | | |
. | | | | |
. | | | | |
. CCW | | | | |
. | | | | |
. ALTERNATIVE | | | | |
. | | | | |
. OFF ---------+ +----------+ +----------+ +-----
. SWB | | | | | | | | | |
. | | | | | | | | | |
. ON | +--+ | +--+ | +--+ |
. | | | |
.
.
.
.
. This diagram makes it obvious as to what should be done:
.
.
. Vdd---+---+---+
. | | |
. ** / / / HC4066
. R R R 74HC123 *
. / / / +------------+ +-------+
. ENCODER \ \ \ | | | Y1 |
. +------+ | | | | __ -- | | | CW
. | A |---------------+--| A1 Q1 |------|C1 |
. | | | | | | | | Z1 | SW
. +-| C | | | | | | | |
. | | B |-----------+------| B1 | +-------+
. | +------+ | | | | |
. | | | | | | +-------+
. | +-------+ | | | | | Y2 |
. | | | | | | __ -- | | | CCW
. | +-| | | +--| A2 Q2 |------|C2 |
. | ||----|---+ | | | | Z2 | SW
. +----------| | | | | | | |
. | 2N7000 +---|---|--| B2 | +-------+
. | | | | | |
. | ** === === === | |
. | C| C| C| | CLR1,2 |--'1'
. +----------------+---+---+ +------------+
. |
. --- '123 TIMING ADJUSTED FOR
. /// MINIMUM OUTPUT SWITCH DURATION
.
.
.
.
. * ORIGINAL CIRCUIT SHOWED SW'S NC AND MOMENTARY OPEN
.
. CW SW DOES MOMENTARY OPEN & CCW SW STAYS NC DURING CW ROTN
.
. CCW SW DOES MOMENTARY OPEN & CW SW STAYS NC DURING CCW RTN
.
. **
. R=100K C=0.1U
.
.
.

[Fred Bloggs]

Post by Fred Bloggs
.
.
.
. Vdd---+---+---+
. | | |
. ** / / / HC4066
. R R R 74HC123 *
. / / / +------------+ +-------+
. ENCODER \ \ \ | | | Y1 |
. +------+ | | | | __ -- | | | CW
. | A |---------------+--| A1 Q1 |------|C1 |
. | | | | | | | | Z1 | SW
. +-| C | | | | | | | |
. | | B |-----------+------| B1 | +-------+
. | +------+ | | | | |
. | | | | | | +-------+
. | +-------+ | | | | | Y2 |
. | | | | | | __ -- | | | CCW
. | +-| | | +--| A2 Q2 |------|C2 |
. | ||----|---+ | | | | Z2 | SW
. +----------| | | | | | | |
. | 2N7000 +---|---|--| B2 | +-------+
. | | | | | |
. | ** === === === | |
. | C| C| C| | CLR1,2 |--'1'
. +----------------+---+---+ +------------+
. |
. --- '123 TIMING ADJUSTED FOR
. /// MINIMUM OUTPUT SWITCH DURATION
.

use this:
Please view in a fixed-width font such as Courier.

.
.
. This diagram makes it obvious as to what should be done:
.
.
. Vdd---+------+---+---+
. | | | |
. / ** / / / HC4066
. R R R 470 74HC123 *
. / / / / +------------+ +-------+
. ENCODER \ \ \ \ | | | Y1 |
. +------+ | 10n | | | | __ -- | | | CW
. | A |--+--||----------+--| A1 Q1 |------|C1 |
. | | | | | | | | Z1 | SW
. +-| C | | | | | | | |
. | | B |-------------+------| B1 | +-------+
. | +------+ | | | | |
. | | | | | | +-------+
. | +-------+ | | | | | Y2 |
. | | | | | | __ -- | | | CCW
. | +-| | | +--| A2 Q2 |------|C2 |
. | ||----|---+ | | | Z2 | SW
. +------------| | | | | | |
. | 2N7000 +---|------| B2 | +-------+
. | | | | |
. | ** === === | |
. | C| C| | CLR1,2 |--'1'
. +------------------+---+ +------------+
. |
. --- '123 TIMING ADJUSTED FOR
. /// MINIMUM OUTPUT SWITCH DURATION
.
.
.
.
. * ORIGINAL CIRCUIT SHOWED SW'S NC AND MOMENTARY OPEN
.
. CW SW DOES MOMENTARY OPEN & CCW SW STAYS NC DURING CW ROTN
.
. CCW SW DOES MOMENTARY OPEN & CW SW STAYS NC DURING CCW RTN
.
. **
. R=100K C=0.1U
.
.
.

[Fred Bloggs]

Post by Fred Bloggs

Post by Fred Bloggs
.
.
.
. Vdd---+---+---+
. | | |
. ** / / / HC4066
. R R R 74HC123 *
. / / / +------------+ +-------+
. ENCODER \ \ \ | | | Y1 |
. +------+ | | | | __ -- | | | CW
. | A |---------------+--| A1 Q1 |------|C1 |
. | | | | | | | | Z1 | SW
. +-| C | | | | | | | |
. | | B |-----------+------| B1 | +-------+
. | +------+ | | | | |
. | | | | | | +-------+
. | +-------+ | | | | | Y2 |
. | | | | | | __ -- | | | CCW
. | +-| | | +--| A2 Q2 |------|C2 |
. | ||----|---+ | | | | Z2 | SW
. +----------| | | | | | | |
. | 2N7000 +---|---|--| B2 | +-------+
. | | | | | |
. | ** === === === | |
. | C| C| C| | CLR1,2 |--'1'
. +----------------+---+---+ +------------+
. |
. --- '123 TIMING ADJUSTED FOR
. /// MINIMUM OUTPUT SWITCH DURATION
.

Please view in a fixed-width font such as Courier.
.
.
.
.
. Vdd---+------+---+---+
. | | | |
. / ** / / / HC4066
. R R R 470 74HC123 *
. / / / / +------------+ +-------+
. ENCODER \ \ \ \ | | | Y1 |
. +------+ | 10n | | | | __ -- | | | CW
. | A |--+--||----------+--| A1 Q1 |------|C1 |
. | | | | | | | | Z1 | SW
. +-| C | | | | | | | |
. | | B |-------------+------| B1 | +-------+
. | +------+ | | | | |
. | | | | | | +-------+
. | +-------+ | | | | | Y2 |
. | | | | | | __ -- | | | CCW
. | +-| | | +--| A2 Q2 |------|C2 |
. | ||----|---+ | | | Z2 | SW
. +------------| | | | | | |
. | 2N7000 +---|------| B2 | +-------+
. | | | | |
. | ** === === | |
. | C| C| | CLR1,2 |--'1'
. +------------------+---+ +------------+
. |
. --- '123 TIMING ADJUSTED FOR
. /// MINIMUM OUTPUT SWITCH DURATION
.
.
.
.
. * ORIGINAL CIRCUIT SHOWED SW'S NC AND MOMENTARY OPEN
.
. CW SW DOES MOMENTARY OPEN & CCW SW STAYS NC DURING CW ROTN
.
. CCW SW DOES MOMENTARY OPEN & CW SW STAYS NC DURING CCW RTN
.
. **
. R=100K C=0.1U
.
.
.

By differentiating 'A', it is no longer necessary to debounce 'B'-
monostable statically disabled by /A input:
Please view in a fixed-width font such as Courier.

.
. This diagram makes it obvious as to what should be done:
.
. **
. Vdd---+------+---+---+ R=100K
. | | | | *
. / ** / / / HC4066
. R R R 470 74HC123
. / / / / +------------+ +-------+
. ENCODER \ \ \ \ | | | Y1 |
. +------+ | 10n | | | | __ -- | | | CW
. | A |--+--||----------+--| A1 Q1 |------|C1 |
. | | | | | | | | Z1 | SW
. +-| C | | | | | | | |
. | | B |-------------+------| B1 | +-------+
. | +------+ | | | | |
. | | | | | | +-------+
. | +-------+ | | | | | Y2 |
. | | | | | | __ -- | | | CCW
. | +-| | | +--| A2 Q2 |------|C2 |
. | ||----|---+ | | | Z2 | SW
. +------------| | | | | |
. | 2N7000 +----------| B2 | +-------+
. | | |
. | | |
. | | CLR1,2 |--'1'
. | +------------+
. |
. --- '123 TIMING ADJUSTED FOR
. /// MINIMUM OUTPUT SWITCH DURATION
.
.
.
.
. * ORIGINAL CIRCUIT SHOWED SW'S NC AND MOMENTARY OPEN
.
. CW SW DOES MOMENTARY OPEN & CCW SW STAYS NC DURING CW ROTN
.
. CCW SW DOES MOMENTARY OPEN & CW SW STAYS NC DURING CCW RTN
.
.
.

[Spehro Pefhany]

On Thu, 22 Apr 2004 14:50:01 GMT, the renowned Fred Bloggs

Post by Fred Bloggs
.
.
.
. Vdd---+------+---+---+
. | | | |
. / ** / / / HC4066
. R R R 470 74HC123 *
. / / / / +------------+ +-------+
. ENCODER \ \ \ \ | | | Y1 |
. +------+ | 10n | | | | __ -- | | | CW
. | A |--+--||----------+--| A1 Q1 |------|C1 |
. | | | | | | | | Z1 | SW
. +-| C | | | | | | | |
. | | B |-------------+------| B1 | +-------+
. | +------+ | | | | |
. | | | | | | +-------+
. | +-------+ | | | | | Y2 |
. | | | | | | __ -- | | | CCW
. | +-| | | +--| A2 Q2 |------|C2 |
. | ||----|---+ | | | Z2 | SW
. +------------| | | | | | |
. | 2N7000 +---|------| B2 | +-------+
. | | | | |
. | ** === === | |
. | C| C| | CLR1,2 |--'1'
. +------------------+---+ +------------+
. |
. --- '123 TIMING ADJUSTED FOR
. /// MINIMUM OUTPUT SWITCH DURATION
.
.
.
.
. * ORIGINAL CIRCUIT SHOWED SW'S NC AND MOMENTARY OPEN
.
. CW SW DOES MOMENTARY OPEN & CCW SW STAYS NC DURING CW ROTN
.
. CCW SW DOES MOMENTARY OPEN & CW SW STAYS NC DURING CCW RTN
.
. **
. R=100K C=0.1U
.

Very nice and quite elegant. Thanks, Fred, I've passed it along.

Best regards,
Spehro Pefhany

[petrus bitbyter]

Post by Spehro Pefhany
Hi all,
A hobbyist has asked for help using a mechanical encoder in the
http://pages.interlog.com/~speff/usefulinfo/dec_circuit.pdf
Looks like he's generating up/down pulses to simulate keyboard presses
(using the analog switches) from the quadrature outputs.
The problem is that circuit (he says) works fine with this kind of
http://pages.interlog.com/~speff/usefulinfo/Rotary_Config.jpg
Which has guaranteed high B signal (high means that the mechanical
switch is "closed" in this case) at the detent.
He wants to use it with this type (from me)
http://www.trexon.com/pdfs/trexon_encoder_revA.pdf
Where the B signal can be either high or low at the detent, and may
actually change if the switch is teased.
Normally I'd do this with a microcontroller by sampling the two
signals at a few hundred Hz and monitoring state transitions (legal
and illegal) after debouncing (looking for states stable for a couple
of samples). This works very well and is reliable. I've also done it
by locking out additional changes by latching a bit. Either way works
fine, in C, 8051 ASM or PIC ASM.
Restricted to logic gates and hopefully adding few parts, can anyone
suggest a fix to this circuit that will allow it to work with either
type of encoder?
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"

http://www.trexon.com
http://www.speff.com


Spehro,

Can't find my first reply and I may have missed some others as well thanks
to the quality of the newsserver of my provider. :-(

Nevertheless, after a good nights sleep, some thinking and reading the
available replies I came to the circuit below. The XORs are providing short
clockpulses on each edge that clocks the value of the other signal in a
D-flipflop. You can make the delay somewhat longer by an RC-combination if
required. Bounce does not matter, it only clocks the same data once more.
Some more thinking makes me believe I saw a circuit like this in an Elector
issue. Must be many years ago.

View with fixed font

+---------------+
| | .----. Bo
Ai | __ | +-|D Q|---
---+-+----------| | | | | |
| __ |=1|-|---|-|> |
+---| | +--|__| + + | |
|=1|--+ \ / | |o--
+-|__| X '----'
| / \
| +----------+ + .----. Ao
Bi === | __ +-|D Q|---
--+-------+-----| | | |
| __ |=1|-------|> |
+----| | +-|__| | |
|=1|---+ | |o--
+-|__| '----'
|
|
===
GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de


petrus


---
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[GPG]

Post by petrus bitbyter
Can't find my first reply and I may have missed some others as well thanks
to the quality of the newsserver of my provider. :-(
Nevertheless, after a good nights sleep, some thinking and reading the
available replies I came to the circuit below. The XORs are providing short
clockpulses on each edge that clocks the value of the other signal in a
D-flipflop. You can make the delay somewhat longer by an RC-combination if
required. Bounce does not matter, it only clocks the same data once more.
Some more thinking makes me believe I saw a circuit like this in an Elector
issue. Must be many years ago.
View with fixed font
+---------------+
| | .----. Bo
Ai | __ | +-|D Q|---
---+-+----------| | | | | |
| __ |=1|-|---|-|> |
+---| | +--|__| + + | |
|=1|--+ \ / | |o--
+-|__| X '----'
| / \
| +----------+ + .----. Ao
Bi === | __ +-|D Q|---
--+-------+-----| | | |
| __ |=1|-------|> |
+----| | +-|__| | |
|=1|---+ | |o--
+-|__| '----'
|
|
===
GND

Does not supply directional info.