Discussion:
faster DDS clock
(too old to reply)
john larkin
2024-09-18 21:39:39 UTC
Permalink
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.

Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
Phil Hobbs
2024-09-18 21:56:59 UTC
Permalink
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.

Any asymmetry in the square wave turns into subharmonic jitter.

A 2:1 PLL would probably get my vote.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics
john larkin
2024-09-19 01:44:34 UTC
Permalink
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
Cheers
Phil Hobbs
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Phil Hobbs
2024-09-19 03:28:09 UTC
Permalink
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics
john larkin
2024-09-19 03:57:39 UTC
Permalink
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.

If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.

I don't know if this FPGA could internally clock on both edges.

But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
Lasse Langwadt
2024-09-19 22:30:28 UTC
Permalink
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you ***@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

or ***@330MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

if you opt for the Chinese clone, less than half for ***@240MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
Jan Panteltje
2024-09-20 05:11:38 UTC
Permalink
On a sunny day (Fri, 20 Sep 2024 00:30:28 +0200) it happened Lasse Langwadt
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
Last time I used a R2R DAC on my FPGA .. was only 8 bit though.. video
Loading Image...
bottom board top right, all the resistors...
john larkin
2024-09-20 14:49:01 UTC
Permalink
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
That's cool. I need 4 DDSs so I'd use two of them, but it
is still appealing. It looks like I'll have to use an Efinix T130 FPGA
to get the RAM I need for waveform storage, so I'll have tons of logic
and i/o's to go hard parallel to the DACs.

I could use 10 or 9 or 8 bits if that is easier to route, and the
current outputs dump right into the right kind of filter.

I have a Spice model of a DDS clock generator. I wonder how awful a
lowpass filter I can get away with. CLC? Or even RC?
Post by Lasse Langwadt
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
Bill Sloman
2024-09-20 15:49:47 UTC
Permalink
Post by john larkin
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
That's cool. I need 4 DDSs so I'd use two of them, but it
is still appealing. It looks like I'll have to use an Efinix T130 FPGA
to get the RAM I need for waveform storage, so I'll have tons of logic
and i/o's to go hard parallel to the DACs.
I could use 10 or 9 or 8 bits if that is easier to route, and the
current outputs dump right into the right kind of filter.
I have a Spice model of a DDS clock generator. I wonder how awful a
lowpass filter I can get away with. CLC? Or even RC?
Active RC filters are a lot easier to design than anything involving an
inductor. Close tolerance inductors are rare and expensive when they are
available. 25 MHz calls for fast op amps, but you can find them.

Williams and Taylor is a useful reference - not as user-friendly as Don
Lancaster, but a whole lot more comprehensive. And they do cover finite
impulse response filters.
--
Bill Sloman, Sydney
Lasse Langwadt
2024-09-21 21:56:08 UTC
Permalink
Post by john larkin
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
That's cool. I need 4 DDSs so I'd use two of them, but it
is still appealing. It looks like I'll have to use an Efinix T130 FPGA
to get the RAM I need for waveform storage, so I'll have tons of logic
and i/o's to go hard parallel to the DACs.
you can probably get away with wiring the DAC datalines in parallel and
use separate clock for each DAC, sorta like DDR

use DDR output with the data for each DAC, make the clock for each DAC
use the other DDR outputs, one with 0,1 data the other with 1,0 data
john larkin
2024-09-21 15:42:18 UTC
Permalink
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
Lasse Langwadt
2024-09-22 01:11:53 UTC
Permalink
Post by john larkin
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
john larkin
2024-09-22 01:37:26 UTC
Permalink
Post by Lasse Langwadt
Post by john larkin
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
john larkin
2024-09-22 01:40:49 UTC
Permalink
Post by john larkin
Post by Lasse Langwadt
Post by john larkin
Post by Lasse Langwadt
Post by john larkin
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
Post by Phil Hobbs
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
And why do we have those firehoses of HDMI connectors and cables? Why
not use Ethernet or USB out to a monitor?
Jan Panteltje
2024-09-22 08:45:13 UTC
Permalink
On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin
Post by john larkin
Post by Lasse Langwadt
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
to control brightness for the red green and blue guns.
There are still many analog monitors around.
I still have a nice one in the attic, my personal particle accelerator.
Still used in places:
https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
History:
https://en.wikipedia.org/wiki/Cathode-ray_tube

piglet
2024-09-18 21:58:13 UTC
Permalink
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
How important is it that the duty cycle is 50%?
--
piglet
john larkin
2024-09-19 01:51:17 UTC
Permalink
On Wed, 18 Sep 2024 21:58:13 -0000 (UTC), piglet
Post by piglet
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
How important is it that the duty cycle is 50%?
Not super critical. The product is an arbitrary waveform generator and
a small wobble in the output sample timing won't be noticed.

I'm thinking I can keep the duty cycle close to 50%.

The falling-edge jitter should be about the same as the rising edge
jitter.

A dual DAC would save me a lot of data lines, so maybe I can go from
single-8 to a dual-10 DAC or something.
Chris Jones
2024-09-19 11:49:30 UTC
Permalink
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
Doing that doubling trick when you take a sine wave oscillator and feed
it via a comparator to the reference input of a PLL has a subtle
advantage: Any additive 1/f voltage noise affecting the input stage of
the comparator, or from any buffering stages for the sine wave before it
gets to the comparator, will move the rising and falling edges of the
comparator in opposite directions, and if both the rising and falling
edges are clocking the phase detector of the PLL then the 1/f noise will
cancel out at low frequencies and not make it through the loop filter,
and not cause phase modulation of the RF output from the PLL. It's
really a nice bonus. I guess it wouldn't work so well if the incoming
waveform had asymmetric slew rates.
john larkin
2024-09-19 14:39:50 UTC
Permalink
On Thu, 19 Sep 2024 21:49:30 +1000, Chris Jones
Post by Chris Jones
Post by john larkin
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
Doing that doubling trick when you take a sine wave oscillator and feed
it via a comparator to the reference input of a PLL has a subtle
advantage: Any additive 1/f voltage noise affecting the input stage of
the comparator, or from any buffering stages for the sine wave before it
gets to the comparator, will move the rising and falling edges of the
comparator in opposite directions, and if both the rising and falling
edges are clocking the phase detector of the PLL then the 1/f noise will
cancel out at low frequencies and not make it through the loop filter,
and not cause phase modulation of the RF output from the PLL. It's
really a nice bonus. I guess it wouldn't work so well if the incoming
waveform had asymmetric slew rates.
I can't feed my DDS into a PLL; frequency change has to be
instantaneous, and cover a huge frequency range.

I'm generating waveforms that simulate a geared jet engine, which is a
noisy shakey vibrating thing, so nanoseconds of jitter/phase noise
doesn't matter much.

Using a synthesizer would be great, like an LMX2571... no filters or
comparators needed. $7 and we'd be all done. But it takes way too
much math to program.
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