Post by john larkinOn Wed, 10 Jul 2024 22:50:54 -0000 (UTC), Cursitor Doom
Post by bitrexPost by john larkinPost by bitrexPost by john larkinIf you google use d-flop as one-shot
you get some remarkably silly circuits. Many just swipe from this
http://www.discovercircuits.com/DJ-Circuits/oneshots.htm
<https://www.n5dux.com/ham/files/pdf/
Working%20With%20Monostable%20Multivibrators.pdf>
Post by john larkinPost by bitrexFig 9 is about as simple as it gets. I don't understand why the extra
flop and the low pass and stuff after the button in the link you posted,
it's like they never heard of a passive differentiator before.
Yikes, 36 years old. CD4000B logic.
I like d-flop one-shots because they are fast, truly edge-triggered, and
can be gated with the D input.
But RC feedback into a reset input is risky at best. Some flops simply
won't work that way... they hang up.
Is this in furtherence of your TDR experimentation? I can't think of
anything else a one-shot is useful for.
Phil is doing a TDR project. I'm mostly doing slow precision stuff
lately.
I am planning a few new products, and one is a sort of precision pulse
generator. I was thinking to have the "HIT" flop, the first trigger
recognizer, be the one-shot. But it's easier to put that inside an
FPGA. The problem with FPGAs is time jitter, from all the routing
crosstalk and clock feedthru and ground bounce and power supply
sensitivity. Maybe they can be managed.
Probably not. Signal routing is a problem that's hard to manage if you
don't have lot of control over where the signal goes, and can't add
shielding tracks alongside sensitive signal paths.
Post by john larkinI tested one Xilinx chip for pin-to-pin delay sensitivity vs core
supply voltage. It measured 70 microvolts per picosecond.
I had one famous success when I was in the Netherlands, when I added an
ECL front end to a basically TTL delay generating device. Changing Vcc
levels shifted the output edge by an appreciable fraction of a
nanosecond in the original TTL-only system. Shifting the edge-generation
into ECL and taking the TTL output edge from an ECL-to-TTL converter
reduced the timing jitter to undetectable levels.
Post by john larkinSome people think one-shots are evil, but I like them.
They certainly can be, but they can equally be very useful.
You'd be well advised to look carefully at the emitter coupled
monostable, and work out exactly what it does when it starts generating
it's output pulse.
This isn't trivial
https://ieeexplore.ieee.org/document/1643426
but it is worth doing.
If the two transistors in the simple emitter-coupled monostable are
BFR92A parts it can produce a one nsec wide output pulse. It can also
oscillate if you don't manage the base driving impedance carefully.
Faster parts could do better, but can be even harder to keep stable.
--
Bill Sloman, Sydney
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