Discussion:
Really triangular triangles
(too old to reply)
Phil Hobbs
2012-05-11 14:11:49 UTC
Permalink
Hi all,

So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.

There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.

A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.

The bad news is that the time constants have to be right, which means
they have to be tweaked.

The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.

To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.

However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.

I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.

However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.

The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
of the active devices--1 mA into 4700 pF @ 100V, or something like that.

The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)

Any wisdom?

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
John Larkin
2012-05-11 15:53:39 UTC
Permalink
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
I recall a Tektronix appnote or something, where that lamanted the
quality of capacitors, intentional and otherwise, made of FR4. They
have "hook", which I guess translates to lots of dielectric absorption
or c-vs-f or something. FR4 has a ghastly capacitance TC, too, numbers
like 900 ppm/K. Are you using some fancier laminate?

Can you use air? Like a wire or plate bridge over your input node.

You can make a very linear ramp in your speed range with a simple
closed-loop current source feeding a good cap through a ferrite bead.
I make ramps that are 10 and 12-bit linear, numbers like 100 volts/us.
0.2 v/us should be easy. Given that, you could go to a very small
value air cap and ramp harder.

What's the parasitic capacitance of that 100M resistor?
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Phil Hobbs
2012-05-11 16:15:42 UTC
Permalink
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
I recall a Tektronix appnote or something, where that lamanted the
quality of capacitors, intentional and otherwise, made of FR4. They
have "hook", which I guess translates to lots of dielectric absorption
or c-vs-f or something. FR4 has a ghastly capacitance TC, too, numbers
like 900 ppm/K. Are you using some fancier laminate?
Can you use air? Like a wire or plate bridge over your input node.
You can make a very linear ramp in your speed range with a simple
closed-loop current source feeding a good cap through a ferrite bead.
I make ramps that are 10 and 12-bit linear, numbers like 100 volts/us.
0.2 v/us should be easy. Given that, you could go to a very small
value air cap and ramp harder.
What's the parasitic capacitance of that 100M resistor?
I'm assuming about 0.1 pF--that's one of the TCs, but any variations
there are tweaked out by the other adjustments.

Just making the ramp is a piece of cake with an integrator + Schmitt,
but even with an ECL or LVDS comparator, I sort of doubt I'll get 1 ns
corners with any reasonable op amp--though maybe I could use that nice
ADA4899 of yours. Good corners will be a big help, because due to the
weird input specs I can't readily hang a pulser on the input, and it
would be nice for the customer to see that it does what I say it will.

Re the capacitor: I remember the "hook" app note, and although hook is
mostly a >1GHz issue, since I'm looking for something pretty, I'd
probably have to worry about that. I was considering using some nice
Rogers material on account of the temperature and humidity problem, but
the air bridge cap idea is a good one--I'll need some electrostatic
shielding anyway, so perhaps I can use one of those little cell phone
shield cans, and drive that. The capacitance would be easier to
calculate, that's for sure, and if all else fails I can measure it.
Might be a good excuse to get a copy of FastCap.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
John Larkin
2012-05-11 18:37:36 UTC
Permalink
On Fri, 11 May 2012 12:15:42 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
I recall a Tektronix appnote or something, where that lamanted the
quality of capacitors, intentional and otherwise, made of FR4. They
have "hook", which I guess translates to lots of dielectric absorption
or c-vs-f or something. FR4 has a ghastly capacitance TC, too, numbers
like 900 ppm/K. Are you using some fancier laminate?
Can you use air? Like a wire or plate bridge over your input node.
You can make a very linear ramp in your speed range with a simple
closed-loop current source feeding a good cap through a ferrite bead.
I make ramps that are 10 and 12-bit linear, numbers like 100 volts/us.
0.2 v/us should be easy. Given that, you could go to a very small
value air cap and ramp harder.
What's the parasitic capacitance of that 100M resistor?
I'm assuming about 0.1 pF--that's one of the TCs, but any variations
there are tweaked out by the other adjustments.
Just making the ramp is a piece of cake with an integrator + Schmitt,
but even with an ECL or LVDS comparator, I sort of doubt I'll get 1 ns
corners with any reasonable op amp--though maybe I could use that nice
ADA4899 of yours. Good corners will be a big help, because due to the
weird input specs I can't readily hang a pulser on the input, and it
would be nice for the customer to see that it does what I say it will.
Re the capacitor: I remember the "hook" app note, and although hook is
mostly a >1GHz issue, since I'm looking for something pretty, I'd
probably have to worry about that. I was considering using some nice
Rogers material on account of the temperature and humidity problem, but
the air bridge cap idea is a good one--I'll need some electrostatic
shielding anyway, so perhaps I can use one of those little cell phone
shield cans, and drive that. The capacitance would be easier to
calculate, that's for sure, and if all else fails I can measure it.
Might be a good excuse to get a copy of FastCap.
Cheers
Phil Hobbs
Somebody, IRC maybe, makes a surface-mount manganin shunt resistor
that - cool - looks like an Omega. That could hop right over your
signal node and be the shield/cap. And Fotofab will make any shield
you want.
--
John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Nico Coesel
2012-05-11 19:08:07 UTC
Permalink
Post by John Larkin
On Fri, 11 May 2012 12:15:42 -0400, Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Somebody, IRC maybe, makes a surface-mount manganin shunt resistor
that - cool - looks like an Omega. That could hop right over your
signal node and be the shield/cap. And Fotofab will make any shield
you want.
Interesting. Wouldn't any surface mount resistor suffice though? Or is
the ceramic carrier a bad dielectric?
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
***@nctdevpuntnl (punt=.)
--------------------------------------------------------------
Phil Hobbs
2012-05-12 15:09:38 UTC
Permalink
Post by Nico Coesel
Post by John Larkin
On Fri, 11 May 2012 12:15:42 -0400, Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Somebody, IRC maybe, makes a surface-mount manganin shunt resistor
that - cool - looks like an Omega. That could hop right over your
signal node and be the shield/cap. And Fotofab will make any shield
you want.
Interesting. Wouldn't any surface mount resistor suffice though? Or is
the ceramic carrier a bad dielectric?
Alumina has an effective dielectric constant of about 10, so any
variation in the resistor's height above the board, due e.g. to
different solder volume, translates into a big capacitance variation.

I think I found the ones John is talking about,
http://www.vishay.com/docs/30176/wslp3921.pdf . The capacitance would
be in the right range, but I'd have to put an extra quarter inch worth
of trace on the front end, which I'd rather avoid.

I might use one of the nice little poptop shields from Laird, e.g.
http://tinyurl.com/btetcpe , which have gaps where I can escape the
signal traces on Layer 1.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
k***@att.bizzzzzzzzzzzz
2012-05-12 17:23:51 UTC
Permalink
On Sat, 12 May 2012 11:09:38 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Nico Coesel
Post by John Larkin
On Fri, 11 May 2012 12:15:42 -0400, Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Somebody, IRC maybe, makes a surface-mount manganin shunt resistor
that - cool - looks like an Omega. That could hop right over your
signal node and be the shield/cap. And Fotofab will make any shield
you want.
Interesting. Wouldn't any surface mount resistor suffice though? Or is
the ceramic carrier a bad dielectric?
Alumina has an effective dielectric constant of about 10, so any
variation in the resistor's height above the board, due e.g. to
different solder volume, translates into a big capacitance variation.
But the void is not alumina, rather air (e=1).
Post by Phil Hobbs
I think I found the ones John is talking about,
http://www.vishay.com/docs/30176/wslp3921.pdf . The capacitance would
be in the right range, but I'd have to put an extra quarter inch worth
of trace on the front end, which I'd rather avoid.
Huh, I just put a few of those in a design but had never seen even a picture
of one before. I thought they'd just look like a regular SMT resistor.
Post by Phil Hobbs
I might use one of the nice little poptop shields from Laird, e.g.
http://tinyurl.com/btetcpe , which have gaps where I can escape the
signal traces on Layer 1.
Neat. I could have used those in a previous life. The CPoE has custom
shields made.
Phil Hobbs
2012-05-12 19:11:29 UTC
Permalink
Post by k***@att.bizzzzzzzzzzzz
On Sat, 12 May 2012 11:09:38 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Nico Coesel
Post by John Larkin
On Fri, 11 May 2012 12:15:42 -0400, Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Somebody, IRC maybe, makes a surface-mount manganin shunt resistor
that - cool - looks like an Omega. That could hop right over your
signal node and be the shield/cap. And Fotofab will make any shield
you want.
Interesting. Wouldn't any surface mount resistor suffice though? Or is
the ceramic carrier a bad dielectric?
Alumina has an effective dielectric constant of about 10, so any
variation in the resistor's height above the board, due e.g. to
different solder volume, translates into a big capacitance variation.
But the void is not alumina, rather air (e=1).
Right. It works like a gap in a ferrite core, so variations in its
thickness get multiplied by 10 when computing the variation in
capacitance.
Post by k***@att.bizzzzzzzzzzzz
Post by Phil Hobbs
I think I found the ones John is talking about,
http://www.vishay.com/docs/30176/wslp3921.pdf . The capacitance would
be in the right range, but I'd have to put an extra quarter inch worth
of trace on the front end, which I'd rather avoid.
Huh, I just put a few of those in a design but had never seen even a picture
of one before. I thought they'd just look like a regular SMT resistor.
Post by Phil Hobbs
I might use one of the nice little poptop shields from Laird, e.g.
http://tinyurl.com/btetcpe , which have gaps where I can escape the
signal traces on Layer 1.
Neat. I could have used those in a previous life. The CPoE has custom
shields made.
I could do that too, but I'm not a mechanical CAD guy, and this is a lab
gizmo (a front end for a biochip for DNA sequencing).

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Tim Williams
2012-05-12 20:02:54 UTC
Permalink
Post by Phil Hobbs
Post by k***@att.bizzzzzzzzzzzz
Post by Phil Hobbs
Alumina has an effective dielectric constant of about 10, so any
variation in the resistor's height above the board, due e.g. to
different solder volume, translates into a big capacitance variation.
But the void is not alumina, rather air (e=1).
Right. It works like a gap in a ferrite core, so variations in its
thickness get multiplied by 10 when computing the variation in
capacitance.
In a manner of speaking.. To be precise, total capacitance / inductance (as
effective air length) looks like 1 / (l_e/mu + w) where l_e is path length
in the medium (thickness of alumina / length of core), mu is
perm(ittivity/eability) and w is the air gap length. The factor of ten is
in comparing the lengths to each other, but not necessarily the total
capacitance or sensitivity (when gap is very small, C ~ constant; when gap
is larger, C ~ 1/w).


Yet another possibility: print a couple PCBs and stack them as shielding.
Top of the stack is a solid ground plane, with pads around the periphery to
stitch it. Middle layers are "hollow" boards, which can be easily made by
routing out most of the area, providing clearance for components. These
also get pads around the perimeter.

You could make symmetrical stripline this way, by sandwiching the main board
(with solid ground plane on the back, and signal/components on the top)
against another (with just a ground plane, and lots of vias to stitch it,
and routes to provide clearance for components). The boards could even be
epoxied together to fill the air gap.

All these things with PCBs have the same awful tempco, which isn't
necessarily a bad thing if you can compensate with the same or an equivalent
tempco...

Tim
--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Phil Hobbs
2012-05-12 22:47:54 UTC
Permalink
Post by Tim Williams
Post by Phil Hobbs
Post by k***@att.bizzzzzzzzzzzz
Post by Phil Hobbs
Alumina has an effective dielectric constant of about 10, so any
variation in the resistor's height above the board, due e.g. to
different solder volume, translates into a big capacitance variation.
But the void is not alumina, rather air (e=1).
Right. It works like a gap in a ferrite core, so variations in its
thickness get multiplied by 10 when computing the variation in
capacitance.
In a manner of speaking.. To be precise, total capacitance / inductance (as
effective air length) looks like 1 / (l_e/mu + w) where l_e is path length
in the medium (thickness of alumina / length of core), mu is
perm(ittivity/eability) and w is the air gap length. The factor of ten is
in comparing the lengths to each other, but not necessarily the total
capacitance or sensitivity (when gap is very small, C ~ constant; when gap
is larger, C ~ 1/w).
Yet another possibility: print a couple PCBs and stack them as shielding.
Top of the stack is a solid ground plane, with pads around the periphery to
stitch it. Middle layers are "hollow" boards, which can be easily made by
routing out most of the area, providing clearance for components. These
also get pads around the perimeter.
You could make symmetrical stripline this way, by sandwiching the main board
(with solid ground plane on the back, and signal/components on the top)
against another (with just a ground plane, and lots of vias to stitch it,
and routes to provide clearance for components). The boards could even be
epoxied together to fill the air gap.
All these things with PCBs have the same awful tempco, which isn't
necessarily a bad thing if you can compensate with the same or an equivalent
tempco...
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--only the CTE of the shield would matter, which will be in
the 10 ppm/K range. (There would be a second-order effect due to the TC
of the FR4 changing the fringing fields a bit, but that'll be much less
than the TC of the FR4 itself.)

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-12 22:49:30 UTC
Permalink
Phil Hobbs wrote:


[...]
Post by Phil Hobbs
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--
Not in New York. There people only trust air when they can see it :-)

[...]
--
Regards, Joerg

http://www.analogconsultants.com/
Phil Hobbs
2012-05-12 22:51:14 UTC
Permalink
Post by Joerg
[...]
Post by Phil Hobbs
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--
Not in New York. There people only trust air when they can see it :-)
You'd have to be able to swim in it for it to get up to 900 ppm/K!

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Jim Thompson
2012-05-12 23:01:12 UTC
Permalink
Post by Joerg
[...]
Post by Phil Hobbs
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--
Not in New York. There people only trust air when they can see it :-)
[...]
From the way they drive, I didn't know they could see ;-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
Tim Williams
2012-05-13 08:30:55 UTC
Permalink
Post by Phil Hobbs
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--only the CTE of the shield would matter, which will be in
the 10 ppm/K range. (There would be a second-order effect due to the TC
of the FR4 changing the fringing fields a bit, but that'll be much less
than the TC of the FR4 itself.)
But how much mismatch would you expect? Hmm, it'll depend on geometry too,
since copper is different from FR4. Could engineer some amazing
hair-pullers with the conspiracy between linear and flexural CTE there. ;-)

Tim
--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Phil Hobbs
2012-05-13 19:38:12 UTC
Permalink
Post by Tim Williams
Post by Phil Hobbs
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--only the CTE of the shield would matter, which will be in
the 10 ppm/K range. (There would be a second-order effect due to the TC
of the FR4 changing the fringing fields a bit, but that'll be much less
than the TC of the FR4 itself.)
But how much mismatch would you expect? Hmm, it'll depend on geometry too,
since copper is different from FR4. Could engineer some amazing
hair-pullers with the conspiracy between linear and flexural CTE there. ;-)
Air's TC of epsilon is roughly 0.2 ppm/K.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Spehro Pefhany
2012-05-14 01:28:21 UTC
Permalink
On Sun, 13 May 2012 15:38:12 -0400, the renowned Phil Hobbs
Post by Phil Hobbs
Post by Tim Williams
Post by Phil Hobbs
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--only the CTE of the shield would matter, which will be in
the 10 ppm/K range. (There would be a second-order effect due to the TC
of the FR4 changing the fringing fields a bit, but that'll be much less
than the TC of the FR4 itself.)
But how much mismatch would you expect? Hmm, it'll depend on geometry too,
since copper is different from FR4. Could engineer some amazing
hair-pullers with the conspiracy between linear and flexural CTE there. ;-)
Air's TC of epsilon is roughly 0.2 ppm/K.
Cheers
Phil Hobbs
That's a very low number.

My reference says 2ppm/K for dry air, and more typically 5ppm/K (plus
variations for RH and pressure, of course).


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
***@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Phil Hobbs
2012-05-14 02:24:33 UTC
Permalink
Post by Spehro Pefhany
On Sun, 13 May 2012 15:38:12 -0400, the renowned Phil Hobbs
Post by Phil Hobbs
Post by Tim Williams
Post by Phil Hobbs
But cancellation leaves you vulnerable to mismatch, whereas air is
pretty stable--only the CTE of the shield would matter, which will be in
the 10 ppm/K range. (There would be a second-order effect due to the TC
of the FR4 changing the fringing fields a bit, but that'll be much less
than the TC of the FR4 itself.)
But how much mismatch would you expect? Hmm, it'll depend on geometry too,
since copper is different from FR4. Could engineer some amazing
hair-pullers with the conspiracy between linear and flexural CTE there. ;-)
Air's TC of epsilon is roughly 0.2 ppm/K.
Cheers
Phil Hobbs
That's a very low number.
My reference says 2ppm/K for dry air, and more typically 5ppm/K (plus
variations for RH and pressure, of course).
Thanks--I was thinking of the optical response, but of course there are
a bunch of resonances below that. Still a lot lower than the probable
uncertainty of a 900 ppm/K epoxy.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
l***@fonz.dk
2012-05-12 15:49:18 UTC
Permalink
Post by Phil Hobbs
Post by Nico Coesel
Post by John Larkin
On Fri, 11 May 2012 12:15:42 -0400, Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed.  I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode.  Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10.  A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Somebody, IRC maybe, makes a surface-mount manganin shunt resistor
that - cool - looks like an Omega. That could hop right over your
signal node and be the shield/cap. And Fotofab will make any shield
you want.
Interesting. Wouldn't any surface mount resistor suffice though? Or is
the ceramic carrier a bad dielectric?
Alumina has an effective dielectric constant of about 10, so any
variation in the resistor's height above the board, due e.g. to
different solder volume, translates into a big capacitance variation.
but any variation in the resistor's height above the board with only
change
the amount of air under it, the thickness of alumina won't change

-Lasse
unknown
2012-05-11 20:59:13 UTC
Permalink
Post by Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
I recall a Tektronix appnote or something, where that lamanted the
quality of capacitors, intentional and otherwise, made of FR4. They
have "hook", which I guess translates to lots of dielectric absorption
or c-vs-f or something. FR4 has a ghastly capacitance TC, too, numbers
like 900 ppm/K. Are you using some fancier laminate?
Can you use air? Like a wire or plate bridge over your input node.
You can make a very linear ramp in your speed range with a simple
closed-loop current source feeding a good cap through a ferrite bead.
I make ramps that are 10 and 12-bit linear, numbers like 100 volts/us.
0.2 v/us should be easy. Given that, you could go to a very small
value air cap and ramp harder.
What's the parasitic capacitance of that 100M resistor?
I'm assuming about 0.1 pF--that's one of the TCs, but any variations
there are tweaked out by the other adjustments.
Just making the ramp is a piece of cake with an integrator + Schmitt,
but even with an ECL or LVDS comparator, I sort of doubt I'll get 1 ns
corners with any reasonable op amp--though maybe I could use that nice
ADA4899 of yours. Good corners will be a big help, because due to the
weird input specs I can't readily hang a pulser on the input, and it
would be nice for the customer to see that it does what I say it will.
Re the capacitor: I remember the "hook" app note, and although hook is
mostly a >1GHz issue, since I'm looking for something pretty, I'd
probably have to worry about that. I was considering using some nice
Rogers material on account of the temperature and humidity problem, but
the air bridge cap idea is a good one--I'll need some electrostatic
shielding anyway, so perhaps I can use one of those little cell phone
shield cans, and drive that. The capacitance would be easier to
calculate, that's for sure, and if all else fails I can measure it.
Might be a good excuse to get a copy of FastCap.
Cheers
Phil Hobbs
How long are your time constants? IOW how long do you want your pulse to
be, or how much amplitude does you saw tooth need to be? Did you really
mean 100V excursion? That'll be pretty tough with your 1ns requirement.
--
Thanks,
Fred.
Phil Hobbs
2012-05-12 15:12:38 UTC
Permalink
Post by unknown
Post by Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
I recall a Tektronix appnote or something, where that lamanted the
quality of capacitors, intentional and otherwise, made of FR4. They
have "hook", which I guess translates to lots of dielectric absorption
or c-vs-f or something. FR4 has a ghastly capacitance TC, too, numbers
like 900 ppm/K. Are you using some fancier laminate?
Can you use air? Like a wire or plate bridge over your input node.
You can make a very linear ramp in your speed range with a simple
closed-loop current source feeding a good cap through a ferrite bead.
I make ramps that are 10 and 12-bit linear, numbers like 100 volts/us.
0.2 v/us should be easy. Given that, you could go to a very small
value air cap and ramp harder.
What's the parasitic capacitance of that 100M resistor?
I'm assuming about 0.1 pF--that's one of the TCs, but any variations
there are tweaked out by the other adjustments.
Just making the ramp is a piece of cake with an integrator + Schmitt,
but even with an ECL or LVDS comparator, I sort of doubt I'll get 1 ns
corners with any reasonable op amp--though maybe I could use that nice
ADA4899 of yours. Good corners will be a big help, because due to the
weird input specs I can't readily hang a pulser on the input, and it
would be nice for the customer to see that it does what I say it will.
Re the capacitor: I remember the "hook" app note, and although hook is
mostly a >1GHz issue, since I'm looking for something pretty, I'd
probably have to worry about that. I was considering using some nice
Rogers material on account of the temperature and humidity problem, but
the air bridge cap idea is a good one--I'll need some electrostatic
shielding anyway, so perhaps I can use one of those little cell phone
shield cans, and drive that. The capacitance would be easier to
calculate, that's for sure, and if all else fails I can measure it.
Might be a good excuse to get a copy of FastCap.
Cheers
Phil Hobbs
How long are your time constants? IOW how long do you want your pulse to
be, or how much amplitude does you saw tooth need to be? Did you really
mean 100V excursion? That'll be pretty tough with your 1ns requirement.
No, a volt or so would be fine, i.e. a 5 us ramp at 0.2 V/us, but it
needs to be asymmetrical so as to have long enough recovery time for the
tails at different time constants to look different. Something like 5
us up / 50 us down would be ideal.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Bill Sloman
2012-05-11 16:52:44 UTC
Permalink
On May 11, 6:15 pm, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed.  I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode.  Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10.  A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end.  It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output.  This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached.  In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample.  So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily.  The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling.  At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number.  A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant.  (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
I recall a Tektronix appnote or something, where that lamanted the
quality of capacitors, intentional and otherwise, made of FR4. They
have "hook", which I guess translates to lots of dielectric absorption
or c-vs-f or something. FR4 has a ghastly capacitance TC, too, numbers
like 900 ppm/K. Are you using some fancier laminate?
Can you use air? Like a wire or plate bridge over your input node.
You can make a very linear ramp in your speed range with a simple
closed-loop current source feeding a good cap through a ferrite bead.
I make ramps that are 10 and 12-bit linear, numbers like 100 volts/us.
0.2 v/us should be easy. Given that, you could go to a very small
value air cap and ramp harder.
What's the parasitic capacitance of that 100M resistor?
I'm assuming about 0.1 pF--that's one of the TCs, but any variations
there are tweaked out by the other adjustments.
Just making the ramp is a piece of cake with an integrator + Schmitt,
but even with an ECL or LVDS comparator, I sort of doubt I'll get 1 ns
corners with any reasonable op amp--though maybe I could use that nice
ADA4899 of yours.  Good corners will be a big help, because due to the
weird input specs I can't readily hang a pulser on the input, and it
would be nice for the customer to see that it does what I say it will.
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.

Linearity will be controlled by the voltage excursion you allow.You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.

<snip>

--
Bill Sloman, Nijmegen
John Larkin
2012-05-11 23:35:43 UTC
Permalink
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Speaking of phemts and singing and stuff, I did this fast pulse
generator that uses a linear ramp and a couple of comparators to make
a delay-and-width thing. It has three ramp ranges, 2.5/25/250 ns. I
use an NE3509 phemt to discharge the ramp; we discussed the gate level
shifter here a while back. The gate is driven by an EclipsPlus
flipflop.

Well, it worked like hell. There was ringing all over the place,
multiple edges, weird nastiness. I guess the phemt was turning on too
fast, too hard, maybe oscillating a bit. So I stuck a 1.2K 0402
resistor in the gate, and now it's beautiful.

Loading Image...

What a pain. It took me a half hour or so to hack that resistor in.

Surprisingly, the overall insertion delay of the gadget didn't change
enough to notice.

Loading Image...

Loading Image...
--
John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Phil Hobbs
2012-05-12 15:49:42 UTC
Permalink
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Speaking of phemts and singing and stuff, I did this fast pulse
generator that uses a linear ramp and a couple of comparators to make
a delay-and-width thing. It has three ramp ranges, 2.5/25/250 ns. I
use an NE3509 phemt to discharge the ramp; we discussed the gate level
shifter here a while back. The gate is driven by an EclipsPlus
flipflop.
Well, it worked like hell. There was ringing all over the place,
multiple edges, weird nastiness. I guess the phemt was turning on too
fast, too hard, maybe oscillating a bit. So I stuck a 1.2K 0402
resistor in the gate, and now it's beautiful.
http://dl.dropbox.com/u/53724080/Circuits/T240_Gate_Kluge.JPG
What a pain. It took me a half hour or so to hack that resistor in.
Surprisingly, the overall insertion delay of the gadget didn't change
enough to notice.
http://dl.dropbox.com/u/53724080/Circuits/T240_700_ps.jpg
http://dl.dropbox.com/u/53724080/Circuits/T240_100_ps.JPG
Interesting. So maybe a differential-output ECL comparator driving a
pHEMT diff pair, with a couple of current sources and several NPO caps
from the outside of the shield to ground, doubling as RF bypasses.

I have bipolar supplies, so that's not too hard to do on the sink side.
All I need then is a stiff, high-Z current source with good transient
response. (Unfortunately all the good transistors are NPN or
N-channel.) Maybe one of your op amp + flying voltage reference gizmos,
with one of those nice Coilcraft BCR conical inductors in series to
improve the corners. (It wouldn't really need anything that good, but
I've been wanting an excuse to try them, and they'd certainly do the
job.)

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
John Larkin
2012-05-12 19:06:16 UTC
Permalink
On Sat, 12 May 2012 11:49:42 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Speaking of phemts and singing and stuff, I did this fast pulse
generator that uses a linear ramp and a couple of comparators to make
a delay-and-width thing. It has three ramp ranges, 2.5/25/250 ns. I
use an NE3509 phemt to discharge the ramp; we discussed the gate level
shifter here a while back. The gate is driven by an EclipsPlus
flipflop.
Well, it worked like hell. There was ringing all over the place,
multiple edges, weird nastiness. I guess the phemt was turning on too
fast, too hard, maybe oscillating a bit. So I stuck a 1.2K 0402
resistor in the gate, and now it's beautiful.
http://dl.dropbox.com/u/53724080/Circuits/T240_Gate_Kluge.JPG
What a pain. It took me a half hour or so to hack that resistor in.
Surprisingly, the overall insertion delay of the gadget didn't change
enough to notice.
http://dl.dropbox.com/u/53724080/Circuits/T240_700_ps.jpg
http://dl.dropbox.com/u/53724080/Circuits/T240_100_ps.JPG
Interesting. So maybe a differential-output ECL comparator driving a
pHEMT diff pair, with a couple of current sources and several NPO caps
from the outside of the shield to ground, doubling as RF bypasses.
That sounds pretty good. All those caps would keep ringing down. I
have another driver idea that I'll email to you.
Post by Phil Hobbs
I have bipolar supplies, so that's not too hard to do on the sink side.
All I need then is a stiff, high-Z current source with good transient
response. (Unfortunately all the good transistors are NPN or
N-channel.) Maybe one of your op amp + flying voltage reference gizmos,
with one of those nice Coilcraft BCR conical inductors in series to
improve the corners. (It wouldn't really need anything that good, but
I've been wanting an excuse to try them, and they'd certainly do the
job.)
I really would like a good "output stage" like that, namely a phemt
diff pair, current-steering mode, programmable amplitude and DC
offset. I tried it a couple of times and made oscillators. Discretes
are maybe just too big, with too much parasitic inductance, to work. I
do intend to try again soon.

The conicals are impressive, but they are wound with, like, #40 wire,
so they are delicate and hard to handle. Several people make them
now... I guess the Piconics patents timed out.

Some day I'd like to make a benchtop pulse generator, something to
compete with the Agilent and PSPL boxes.

Check the price on this:

http://tinyurl.com/38udh36

It only puts out 2 volts p-p, with 60 ps edges.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Phil Hobbs
2012-05-12 19:18:46 UTC
Permalink
Post by John Larkin
On Sat, 12 May 2012 11:49:42 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Speaking of phemts and singing and stuff, I did this fast pulse
generator that uses a linear ramp and a couple of comparators to make
a delay-and-width thing. It has three ramp ranges, 2.5/25/250 ns. I
use an NE3509 phemt to discharge the ramp; we discussed the gate level
shifter here a while back. The gate is driven by an EclipsPlus
flipflop.
Well, it worked like hell. There was ringing all over the place,
multiple edges, weird nastiness. I guess the phemt was turning on too
fast, too hard, maybe oscillating a bit. So I stuck a 1.2K 0402
resistor in the gate, and now it's beautiful.
http://dl.dropbox.com/u/53724080/Circuits/T240_Gate_Kluge.JPG
What a pain. It took me a half hour or so to hack that resistor in.
Surprisingly, the overall insertion delay of the gadget didn't change
enough to notice.
http://dl.dropbox.com/u/53724080/Circuits/T240_700_ps.jpg
http://dl.dropbox.com/u/53724080/Circuits/T240_100_ps.JPG
Interesting. So maybe a differential-output ECL comparator driving a
pHEMT diff pair, with a couple of current sources and several NPO caps
from the outside of the shield to ground, doubling as RF bypasses.
That sounds pretty good. All those caps would keep ringing down. I
have another driver idea that I'll email to you.
Post by Phil Hobbs
I have bipolar supplies, so that's not too hard to do on the sink side.
All I need then is a stiff, high-Z current source with good transient
response. (Unfortunately all the good transistors are NPN or
N-channel.) Maybe one of your op amp + flying voltage reference gizmos,
with one of those nice Coilcraft BCR conical inductors in series to
improve the corners. (It wouldn't really need anything that good, but
I've been wanting an excuse to try them, and they'd certainly do the
job.)
I really would like a good "output stage" like that, namely a phemt
diff pair, current-steering mode, programmable amplitude and DC
offset. I tried it a couple of times and made oscillators. Discretes
are maybe just too big, with too much parasitic inductance, to work. I
do intend to try again soon.
The conicals are impressive, but they are wound with, like, #40 wire,
so they are delicate and hard to handle. Several people make them
now... I guess the Piconics patents timed out.
Some day I'd like to make a benchtop pulse generator, something to
compete with the Agilent and PSPL boxes.
http://tinyurl.com/38udh36
It only puts out 2 volts p-p, with 60 ps edges.
Yeeouch, $80k! I get better edges than that with an SD-24 and a Mini
Circuits RF amp. Makes a great laser driver for lab purposes.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Phil Hobbs
2012-05-12 23:13:56 UTC
Permalink
Post by John Larkin
On Sat, 12 May 2012 11:49:42 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Fri, 11 May 2012 10:11:49 -0400, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
Speaking of phemts and singing and stuff, I did this fast pulse
generator that uses a linear ramp and a couple of comparators to make
a delay-and-width thing. It has three ramp ranges, 2.5/25/250 ns. I
use an NE3509 phemt to discharge the ramp; we discussed the gate level
shifter here a while back. The gate is driven by an EclipsPlus
flipflop.
Well, it worked like hell. There was ringing all over the place,
multiple edges, weird nastiness. I guess the phemt was turning on too
fast, too hard, maybe oscillating a bit. So I stuck a 1.2K 0402
resistor in the gate, and now it's beautiful.
http://dl.dropbox.com/u/53724080/Circuits/T240_Gate_Kluge.JPG
What a pain. It took me a half hour or so to hack that resistor in.
Surprisingly, the overall insertion delay of the gadget didn't change
enough to notice.
http://dl.dropbox.com/u/53724080/Circuits/T240_700_ps.jpg
http://dl.dropbox.com/u/53724080/Circuits/T240_100_ps.JPG
Interesting. So maybe a differential-output ECL comparator driving a
pHEMT diff pair, with a couple of current sources and several NPO caps
from the outside of the shield to ground, doubling as RF bypasses.
That sounds pretty good. All those caps would keep ringing down. I
have another driver idea that I'll email to you.
Post by Phil Hobbs
I have bipolar supplies, so that's not too hard to do on the sink side.
All I need then is a stiff, high-Z current source with good transient
response. (Unfortunately all the good transistors are NPN or
N-channel.) Maybe one of your op amp + flying voltage reference gizmos,
with one of those nice Coilcraft BCR conical inductors in series to
improve the corners. (It wouldn't really need anything that good, but
I've been wanting an excuse to try them, and they'd certainly do the
job.)
I really would like a good "output stage" like that, namely a phemt
diff pair, current-steering mode, programmable amplitude and DC
offset. I tried it a couple of times and made oscillators. Discretes
are maybe just too big, with too much parasitic inductance, to work. I
do intend to try again soon.
The conicals are impressive, but they are wound with, like, #40 wire,
so they are delicate and hard to handle. Several people make them
now... I guess the Piconics patents timed out.
The Coilcraft ones are pretty nice that way--they have a U-shaped shroud
and metal alloy end caps, so they work with pick and place. I have a
RFQ in--it looks like they haven't decided what to charge for them.

http://www.coilcraft.com/bcr.cfm

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-12 16:56:15 UTC
Permalink
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
AFAIU you want to match the gain of a low frequency path to a high
frequency path. Can't you just use a generator that sends out two or
more frequencies? Save you the expensive opamps and whatnot in a fast
ramperoo circuit.
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
If it really has to be ramps and you need opamps, consider these:

http://www.ti.com/lit/ds/symlink/ths4303.pdf

I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
--
Regards, Joerg

http://www.analogconsultants.com/
Phil Hobbs
2012-05-12 19:28:59 UTC
Permalink
Post by Joerg
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
AFAIU you want to match the gain of a low frequency path to a high
frequency path. Can't you just use a generator that sends out two or
more frequencies? Save you the expensive opamps and whatnot in a fast
ramperoo circuit.
This is a research project for DNA sequencing, so parts cost is almost
irrelevant. Plus the step response is a key parameter, and (owing to
the weird input specs) would be very difficult for non-circuits folks to
measure accurately. I'm completely happy for the BIST to cost $50 per
board if necessary.
Post by Joerg
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
http://www.ti.com/lit/ds/symlink/ths4303.pdf
I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
I can easily imagine. Since I don't get to supervise the layout,
something slightly tamer would probably be best. Nice part though.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-12 19:42:10 UTC
Permalink
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
AFAIU you want to match the gain of a low frequency path to a high
frequency path. Can't you just use a generator that sends out two or
more frequencies? Save you the expensive opamps and whatnot in a fast
ramperoo circuit.
This is a research project for DNA sequencing, so parts cost is almost
irrelevant. Plus the step response is a key parameter, and (owing to
the weird input specs) would be very difficult for non-circuits folks to
measure accurately. I'm completely happy for the BIST to cost $50 per
board if necessary.
A frequency domain measurement with fat amplitudes can ascertain time
domain parameters as well. I was just thinking about what might be
easier, not cheaper. But if you ramp gen works, then yeah, why not?
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
http://www.ti.com/lit/ds/symlink/ths4303.pdf
I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
I can easily imagine. Since I don't get to supervise the layout,
something slightly tamer would probably be best. Nice part though.
On this kind of project I'd insist on checking off the layout. Unless
there is a hardcore RF guy doing the layout on their side a major
screw-up would almost be guaranteed otherwise.
--
Regards, Joerg

http://www.analogconsultants.com/
Phil Hobbs
2012-05-12 20:12:58 UTC
Permalink
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
AFAIU you want to match the gain of a low frequency path to a high
frequency path. Can't you just use a generator that sends out two or
more frequencies? Save you the expensive opamps and whatnot in a fast
ramperoo circuit.
This is a research project for DNA sequencing, so parts cost is almost
irrelevant. Plus the step response is a key parameter, and (owing to
the weird input specs) would be very difficult for non-circuits folks to
measure accurately. I'm completely happy for the BIST to cost $50 per
board if necessary.
A frequency domain measurement with fat amplitudes can ascertain time
domain parameters as well. I was just thinking about what might be
easier, not cheaper. But if you ramp gen works, then yeah, why not?
All the plots I'm giving them are time-domain and SNR, and with the ramp
generator they can see if the tweaked system gives them the results they
expect. It's a nice clean demarcation, which is important when your
customer is 14 time zones ahead of you. ;)
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
http://www.ti.com/lit/ds/symlink/ths4303.pdf
I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
I can easily imagine. Since I don't get to supervise the layout,
something slightly tamer would probably be best. Nice part though.
On this kind of project I'd insist on checking off the layout. Unless
there is a hardcore RF guy doing the layout on their side a major
screw-up would almost be guaranteed otherwise.
Yup. I'll get them to send it to me to look at, but I have no idea if
their layout guy speaks good enough English for us to communicate.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-12 20:54:04 UTC
Permalink
[...]
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
http://www.ti.com/lit/ds/symlink/ths4303.pdf
I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
I can easily imagine. Since I don't get to supervise the layout,
something slightly tamer would probably be best. Nice part though.
On this kind of project I'd insist on checking off the layout. Unless
there is a hardcore RF guy doing the layout on their side a major
screw-up would almost be guaranteed otherwise.
Yup. I'll get them to send it to me to look at, but I have no idea if
their layout guy speaks good enough English for us to communicate.
BT. While in Seoul on a noise debug mission one of the engineers asked
me: "What leeshe fuh hey oy won glou in shiste?"

Translating to English English: "What is the reason for having only one
ground in the system?"
--
Regards, Joerg

http://www.analogconsultants.com/
unknown
2012-05-12 21:50:48 UTC
Permalink
Post by Joerg
[...]
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
http://www.ti.com/lit/ds/symlink/ths4303.pdf
I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
I can easily imagine. Since I don't get to supervise the layout,
something slightly tamer would probably be best. Nice part though.
On this kind of project I'd insist on checking off the layout. Unless
there is a hardcore RF guy doing the layout on their side a major
screw-up would almost be guaranteed otherwise.
Yup. I'll get them to send it to me to look at, but I have no idea if
their layout guy speaks good enough English for us to communicate.
BT. While in Seoul on a noise debug mission one of the engineers asked
me: "What leeshe fuh hey oy won glou in shiste?"
Translating to English English: "What is the reason for having only one
ground in the system?"
Then you could try answering in Korean...
--
Thanks,
Fred.
josephkk
2012-05-16 04:19:24 UTC
Permalink
On Sat, 12 May 2012 16:12:58 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
AFAIU you want to match the gain of a low frequency path to a high
frequency path. Can't you just use a generator that sends out two or
more frequencies? Save you the expensive opamps and whatnot in a fast
ramperoo circuit.
This is a research project for DNA sequencing, so parts cost is almost
irrelevant. Plus the step response is a key parameter, and (owing to
the weird input specs) would be very difficult for non-circuits folks to
measure accurately. I'm completely happy for the BIST to cost $50 per
board if necessary.
A frequency domain measurement with fat amplitudes can ascertain time
domain parameters as well. I was just thinking about what might be
easier, not cheaper. But if you ramp gen works, then yeah, why not?
All the plots I'm giving them are time-domain and SNR, and with the ramp
generator they can see if the tweaked system gives them the results they
expect. It's a nice clean demarcation, which is important when your
customer is 14 time zones ahead of you. ;)
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
http://www.ti.com/lit/ds/symlink/ths4303.pdf
I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
I can easily imagine. Since I don't get to supervise the layout,
something slightly tamer would probably be best. Nice part though.
On this kind of project I'd insist on checking off the layout. Unless
there is a hardcore RF guy doing the layout on their side a major
screw-up would almost be guaranteed otherwise.
Yup. I'll get them to send it to me to look at, but I have no idea if
their layout guy speaks good enough English for us to communicate.
Cheers
Phil Hobbs
And you don't hear the meat grinder starting?

?-)
Phil Hobbs
2012-05-16 16:20:41 UTC
Permalink
Post by josephkk
On Sat, 12 May 2012 16:12:58 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
AFAIU you want to match the gain of a low frequency path to a high
frequency path. Can't you just use a generator that sends out two or
more frequencies? Save you the expensive opamps and whatnot in a fast
ramperoo circuit.
This is a research project for DNA sequencing, so parts cost is almost
irrelevant. Plus the step response is a key parameter, and (owing to
the weird input specs) would be very difficult for non-circuits folks to
measure accurately. I'm completely happy for the BIST to cost $50 per
board if necessary.
A frequency domain measurement with fat amplitudes can ascertain time
domain parameters as well. I was just thinking about what might be
easier, not cheaper. But if you ramp gen works, then yeah, why not?
All the plots I'm giving them are time-domain and SNR, and with the ramp
generator they can see if the tweaked system gives them the results they
expect. It's a nice clean demarcation, which is important when your
customer is 14 time zones ahead of you. ;)
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
http://www.ti.com/lit/ds/symlink/ths4303.pdf
I suggested them to a client for a fast fiberoptics thing and it blew
their socks off. Of course, doing the layout is like driving a souped-up
Porsche on a sheet of ice.
I can easily imagine. Since I don't get to supervise the layout,
something slightly tamer would probably be best. Nice part though.
On this kind of project I'd insist on checking off the layout. Unless
there is a hardcore RF guy doing the layout on their side a major
screw-up would almost be guaranteed otherwise.
Yup. I'll get them to send it to me to look at, but I have no idea if
their layout guy speaks good enough English for us to communicate.
Cheers
Phil Hobbs
And you don't hear the meat grinder starting?
?-)
Why? I get paid when I send them the schematic, BOM, and simulations.
Debug is extra, and anyway it isn't going to be that hard, I don't
think--I built a test board that worked fine with only one minor bodge.
It really does pick up everything around, unless I run it inside a
metal box with feedthrough capacitors.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Phil Hobbs
2012-05-13 21:10:21 UTC
Permalink
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.

Just so you don't think I'm ignoring you guys,

(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)

I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.

(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.

It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.

A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.

The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.

(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.

I think the best candidate so far is:
a 1/2-inch square Laird shield for coupling to the input node, connected
to the integration capacitor of a tri wave generator. The integration
cap will actually be something like 10 470 pF @ 100V 0805 NPO caps
between the shield can and the ground plane, which will double as RF
bypasses and keep the ringing down. I don't need the high voltage, of
course, but it'll keep the nonlinearity down to a very low level and
doesn't cost that much extra.

Driving the integration cap are a fixed 1 mA current source consisting
of a fast op amp, a floating reference, two resistors, and a very
wideband bias choke (8 uH) in series with its output, just to crispen up
the corners of the ramps,

and

a steerable 1.1 mA current sink with another op amp and another choke,
steered by a couple of the same pHEMTs as the front end (to keep the BOM
simple) with 1k-ish gate resistors (per JL) to keep them stable. Those
will be driven by an ECL comparator with a bit of positive feedback,
looking at a buffered copy of the voltage on the shield can.

The result should be a 1V p-p ramp with +200 kV/s-ish rise and 20
kV/s-ish fall. With a coupling capacitance of about 0.05 pF, that's a
+10 nA /-1 nA pulse with a period of 55 us and 10% duty cycle. Assuming
the corners are nice and sharp, which they should be, I'll get good
edges and nice flat tops.

The idea is for the customer to be able to hook up a scope, push one
button, and see a pulse response pretty enough to bring a tear to the
eye. ;)

Thanks again,

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-13 21:39:50 UTC
Permalink
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Really weird. I am on a paid server (news.individual.de) and I can see
Fred's posts but not Bill's and not Tim Shoppa's. At least not in this
thread.

[...]
Post by Phil Hobbs
a 1/2-inch square Laird shield for coupling to the input node, connected
to the integration capacitor of a tri wave generator.
You mean the whole Laird shield is whomping? Make sure that all this is
in a metal enclosure and stuff won't leak out via wires. Else the
Federales might be waltzing in some day, worst case at a client.
--
Regards, Joerg

http://www.analogconsultants.com/
Phil Hobbs
2012-05-13 22:17:35 UTC
Permalink
Post by Joerg
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Really weird. I am on a paid server (news.individual.de) and I can see
Fred's posts but not Bill's and not Tim Shoppa's. At least not in this
thread.
[...]
Post by Phil Hobbs
a 1/2-inch square Laird shield for coupling to the input node, connected
to the integration capacitor of a tri wave generator.
You mean the whole Laird shield is whomping? Make sure that all this is
in a metal enclosure and stuff won't leak out via wires. Else the
Federales might be waltzing in some day, worst case at a client.
I sort of doubt that a 1/2 inch square shield with a 19 kHz rectangle
wave on it is going to interest them.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-13 22:58:40 UTC
Permalink
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Really weird. I am on a paid server (news.individual.de) and I can see
Fred's posts but not Bill's and not Tim Shoppa's. At least not in this
thread.
[...]
Post by Phil Hobbs
a 1/2-inch square Laird shield for coupling to the input node, connected
to the integration capacitor of a tri wave generator.
You mean the whole Laird shield is whomping? Make sure that all this is
in a metal enclosure and stuff won't leak out via wires. Else the
Federales might be waltzing in some day, worst case at a client.
I sort of doubt that a 1/2 inch square shield with a 19 kHz rectangle
wave on it is going to interest them.
Depends on how high the harmonics go and how strong they are. I've seen
numerous cases where folks failed class B because a little connector can
was floating. If you deliberately "light it up" it'll get even worse.
Just meant as a friendly hint from a guy who has seen lots of grief when
it comes to EMC :-)

Cases like a little one-line display, only six characters long or so,
maybe 1/2 square-inch. They were sure it won't matter not to ground that
too well. Until the day of reckoning at the EMC lab. Sometimes it's
tough to bite the tongue and not say "told ya so" but as a consultant
one has to keep such thoughts to oneself. The sad part was not so much
the wasted $2k for the lab but it meant a re-layout.
--
Regards, Joerg

http://www.analogconsultants.com/
Phil Hobbs
2012-05-14 00:14:59 UTC
Permalink
Post by Joerg
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Really weird. I am on a paid server (news.individual.de) and I can see
Fred's posts but not Bill's and not Tim Shoppa's. At least not in this
thread.
[...]
Post by Phil Hobbs
a 1/2-inch square Laird shield for coupling to the input node, connected
to the integration capacitor of a tri wave generator.
You mean the whole Laird shield is whomping? Make sure that all this is
in a metal enclosure and stuff won't leak out via wires. Else the
Federales might be waltzing in some day, worst case at a client.
I sort of doubt that a 1/2 inch square shield with a 19 kHz rectangle
wave on it is going to interest them.
Depends on how high the harmonics go and how strong they are. I've seen
numerous cases where folks failed class B because a little connector can
was floating. If you deliberately "light it up" it'll get even worse.
Just meant as a friendly hint from a guy who has seen lots of grief when
it comes to EMC :-)
Cases like a little one-line display, only six characters long or so,
maybe 1/2 square-inch. They were sure it won't matter not to ground that
too well. Until the day of reckoning at the EMC lab. Sometimes it's
tough to bite the tongue and not say "told ya so" but as a consultant
one has to keep such thoughts to oneself. The sad part was not so much
the wasted $2k for the lab but it meant a re-layout.
Understood. But this one is for a research lab, and the little triangle
wave will only be on for 2 minutes while someone is adjusting the TCs.
If I wind up selling something of the same sort elsewhere, it'll
definitely be in a metal box. (Naturally I don't sell the same circuit
to more than one customer, but I've learned a lot doing this one.)

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net
josephkk
2012-05-16 04:31:27 UTC
Permalink
Post by Joerg
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Really weird. I am on a paid server (news.individual.de) and I can see
Fred's posts but not Bill's and not Tim Shoppa's. At least not in this
thread.
Recently, i have been having all kinds of funny things; like many posts
not available any more but replies to it visible. No apparent reason. The
retry nature of Usenet makes this very strange. Normally if you can get
enough header to find the message you can get the message. Very strange.
Very random message drops. And i pay for it.
Post by Joerg
[...]
Post by Phil Hobbs
a 1/2-inch square Laird shield for coupling to the input node, connected
to the integration capacitor of a tri wave generator.
You mean the whole Laird shield is whomping? Make sure that all this is
in a metal enclosure and stuff won't leak out via wires. Else the
Federales might be waltzing in some day, worst case at a client.
Joerg
2012-05-17 15:24:25 UTC
Permalink
Post by josephkk
Post by Joerg
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Really weird. I am on a paid server (news.individual.de) and I can see
Fred's posts but not Bill's and not Tim Shoppa's. At least not in this
thread.
Recently, i have been having all kinds of funny things; like many posts
not available any more but replies to it visible. No apparent reason. The
retry nature of Usenet makes this very strange. Normally if you can get
enough header to find the message you can get the message. Very strange.
Very random message drops. And i pay for it.
What I noticed: Until recently I had to block everything coming in via a
google domain because their spam level was out of control. Occasionally
I took out the filter and put it right back in. Then one day I noticed
that the spam getting being caught and dumped by my own filter had
become miniscule. It seems the server I am using is now hosing off a lot
of that stuff right there, doesn't even get on. Obviously that can
result in the occasional good post being hosed off. That's why I keep
telling people not to use freemail domains. Because their posts may
simply not show up on many news servers.

[...]
--
Regards, Joerg

http://www.analogconsultants.com/
Bill Sloman
2012-05-14 21:23:54 UTC
Permalink
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty well
out of court, e.g. the LT1016. Thanks though.
When I checked the thread through my Forte account, my Google groups
posts weren't there. Here's my response again.

The circuit I posted defined the slope of the 5usec ramp with a
constant current derived from a long-tailed pair of BFR92 transistors.

It's going to be very linear. The slope depends on the current through
the tail. You've got 5V to play with so we could put a current source
in the tail with a precision resistor, and N-FET and an op amp to make
it really well defined. The current gain of the BFR92 ranges from a
minimum of 65 to the typical 90 up to 135, so you could lose as much
as 1.5% of your tail current through the base junction. Bipolar
transistor gain rises with temperature, so this proportion would be
temperature dependent.

If you want something more stable, it might be worth looking at making
the long-tailed pair with two BFRT92/BFR92 complementary Darlingtons;
you'd probably need to jack up the current a bit (and increase the
timing capacitor in proportion) to keep the lower-current part of the
complementary pair tolerably fast.

The 50usec recovery is exponential, with roughly 30uA through R1. You
could make it a constant current source - in the good old days you
could buy selected FETs for use as constant current diodes, but today
it looks as if you'd have to buy a Fairchild J201 and put a resistor
between source and gate.

http://www.fairchildsemi.com/ds/J2/J201.pdf

About 30k would get you of the order of 30uA with a "typical" gate-to-
source cut-off voltage, but you'd have to do select on test to get
anything reliable or usefully predictable.

A PNP current mirror would be easier, but - as usual - you have to
worry about the base current and the Early effect.

You could use a P-channel FET and a rail-to-rail op amp to set up
precise current source. Farnell stock the MMBFJ177 which looks as if
it could be made to work

http://www.onsemi.com/pub_link/Collateral/MMBFJ177LT1-D.PDF

How much you'd have to do to get the degree of predictablity and
flatness that you need rather depends on what numbers you want to
attach to "predictable", "flat" and "temperature independent". There
are well know solutions for every level of accuracy - as you raise
your standards, the components become more numerous and expensive.

E-mail me if you don't want to be explicit in public.
--
Bill Sloman, Nijmegen
Bill Sloman
2012-05-13 22:36:46 UTC
Permalink
On May 13, 11:10 pm, Phil Hobbs
There are a few people posting to this thread (Fred B,BillS and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (BillS)
 >You can make a triangular wave with just a comparator - the comparator
 >output pin generates a square wave, but you generate a triangular wave
 >at the inverting input, and the corners will be as good as the
 >transition times at the output - about 250psec with the MC100EP116.
 >Linearity will be controlled by the voltage excursion you allow.  You
 >will be generating an exponential decays rather than linear ramps, but
 >for a sufficiently small excursion the non-linearity won't be
 >dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output.  That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016.  Thanks though.
The circuit I posted defined the slope of the 5usec ramp with a
constant current derived from a long-tailed pair of BFR92 transistors.

It's going to be very linear. The slope depends on the current through
the tail. You've got 5V to play with so we could put a current source
in the tail with a precision resistor, and N-FET and an op amp to make
it really well defined. The current gain of the BFR92 ranges from a
minimum of 65 to the typical 90 up to 135, so you could lose as much
as 1.5% of your tail current through the base junction. Bipolar
transistor gain rises with temperature, so this proportion would be
temperature dependent.

If you want something more stable, it might be worth looking at making
the long-tailed pair with two BFRT92/BFR92 complementary Darlingtons;
you'd probably need to jack up the current a bit (and increase the
timing capacitor in proportion) to keep the lower-current part of the
complementary pair tolerably fast.

The 50usec recovery is exponential, with roughly 30uA through R1. You
could make it a constant current source - in the good old days you
could buy selected FETs for use as constant current diodes, but today
it looks as if you'd have to buy a Fairchild J201 and put a resistor
between source and gate.

http://www.fairchildsemi.com/ds/J2/J201.pdf

About 30k would get you of the order of 30uA with a "typical" gate-to-
source cut-off voltage, but you'd have to do select on test to get
anything reliable or usefully predictable.

A PNP current mirror would be easier, but - as usual - you have to
worry about the base current and the Early effect.

You could use a P-channel FET and a rail-to-rail op amp to set up
precise current source. Farnell stock the MMBFJ177 which looks as if
it could be made to work

http://www.onsemi.com/pub_link/Collateral/MMBFJ177LT1-D.PDF

How much you'd have to do to get the degree of predictablity and
flatness that you need rather depends on what numbers you want to
attach to "predictable", "flat" and "temperature independent". There
are well know solutions for every level of accuracy - as you raise
your standards, the components become more numerous and expensive.

E-mail me if you don't want to be explicit in public.

--
Bill Sloman, Nijmegen
b***@gmail.com
2012-05-14 01:17:15 UTC
Permalink
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Post by Phil Hobbs
a 1/2-inch square Laird shield for coupling to the input node, connected
to the integration capacitor of a tri wave generator. The integration
between the shield can and the ground plane, which will double as RF
bypasses and keep the ringing down. I don't need the high voltage, of
course, but it'll keep the nonlinearity down to a very low level and
doesn't cost that much extra.
Driving the integration cap are a fixed 1 mA current source consisting
of a fast op amp, a floating reference, two resistors, and a very
wideband bias choke (8 uH) in series with its output, just to crispen up
the corners of the ramps,
and
a steerable 1.1 mA current sink with another op amp and another choke,
steered by a couple of the same pHEMTs as the front end (to keep the BOM
simple) with 1k-ish gate resistors (per JL) to keep them stable. Those
will be driven by an ECL comparator with a bit of positive feedback,
looking at a buffered copy of the voltage on the shield can.
The result should be a 1V p-p ramp with +200 kV/s-ish rise and 20
kV/s-ish fall. With a coupling capacitance of about 0.05 pF, that's a
+10 nA /-1 nA pulse with a period of 55 us and 10% duty cycle. Assuming
the corners are nice and sharp, which they should be, I'll get good
edges and nice flat tops.
The idea is for the customer to be able to hook up a scope, push one
button, and see a pulse response pretty enough to bring a tear to the
eye. ;)
Thanks again,
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Phil Hobbs
2012-05-14 06:47:25 UTC
Permalink
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
 >You can make a triangular wave with just a comparator - the comparator
 >output pin generates a square wave, but you generate a triangular wave
 >at the inverting input, and the corners will be as good as the
 >transition times at the output - about 250psec with the MC100EP116.
 >Linearity will be controlled by the voltage excursion you allow.  You
 >will be generating an exponential decays rather than linear ramps, but
 >for a sufficiently small excursion the non-linearity won't be
 >dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output.  That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016.  Thanks though.
(b) (Tim S)
 >I know you have your heart set on a triangle wave.... but scope and
 >scope probes have allowed users to tweak probe padding compensation
 >with square waves for a long time. This is a tweak that un-EE-
 >sophisticated users do all the time as part of many procedures. Same
 >problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give.  The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application.  This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers.  The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit.  (Easy in a
CCD, but you can't put a wire on a CCD pixel.)  So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts.  Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance.  (The amp is supposed to be current-sensitive anyway.)  The
capacitance of an additional pad is much too large.
(c) (Fred B)
 >If you want really fast edge rates then you're not going to beat
 > working with a square wave (or rectangular in your case) drive of a
 > fast buffer with an RC-analog feedback. Your input source could be an
 > HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be  equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)

I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net
b***@gmail.com
2012-05-14 16:55:23 UTC
Permalink
Post by Phil Hobbs
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
 >You can make a triangular wave with just a comparator - the comparator
 >output pin generates a square wave, but you generate a triangular wave
 >at the inverting input, and the corners will be as good as the
 >transition times at the output - about 250psec with the MC100EP116.
 >Linearity will be controlled by the voltage excursion you allow.  You
 >will be generating an exponential decays rather than linear ramps, but
 >for a sufficiently small excursion the non-linearity won't be
 >dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output.  That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016.  Thanks though.
(b) (Tim S)
 >I know you have your heart set on a triangle wave.... but scope and
 >scope probes have allowed users to tweak probe padding compensation
 >with square waves for a long time. This is a tweak that un-EE-
 >sophisticated users do all the time as part of many procedures. Same
 >problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give.  The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application.  This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers.  The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit.  (Easy in a
CCD, but you can't put a wire on a CCD pixel.)  So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts.  Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance.  (The amp is supposed to be current-sensitive anyway.)  The
capacitance of an additional pad is much too large.
(c) (Fred B)
 >If you want really fast edge rates then you're not going to beat
 > working with a square wave (or rectangular in your case) drive of a
 > fast buffer with an RC-analog feedback. Your input source could be an
 > HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be  equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Phil Hobbs
2012-05-14 23:31:54 UTC
Permalink
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-15 15:12:33 UTC
Permalink
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg

http://www.analogconsultants.com/
Phil Hobbs
2012-05-15 15:39:21 UTC
Permalink
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
John Larkin
2012-05-15 16:18:07 UTC
Permalink
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.

Oh, our EM sims and ground cutouts seem to have worked pretty well on
the edge-launch SMAs. Here's our output pulse:

Loading Image...

That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...

Loading Image...

42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Phil Hobbs
2012-05-15 16:41:43 UTC
Permalink
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.

BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
John Larkin
2012-05-15 16:51:37 UTC
Permalink
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.

You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Phil Hobbs
2012-05-15 16:53:50 UTC
Permalink
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
If that were my only timing problem, I'd be a lot better off than I am
now.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Joerg
2012-05-15 21:55:49 UTC
Permalink
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
--
Regards, Joerg

http://www.analogconsultants.com/
John Larkin
2012-05-15 23:55:23 UTC
Permalink
Post by Joerg
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
I'll have to look into that one of these days. Older LEDs used a lot
of current. Maybe a newer LED and a bigger resistor would fix it. Or
maybe it's not the LED current at all.

It is surprising that Tek apparently never fixed it.
--
John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Joerg
2012-05-16 00:06:46 UTC
Permalink
Post by John Larkin
Post by Joerg
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
I'll have to look into that one of these days. Older LEDs used a lot
of current. Maybe a newer LED and a bigger resistor would fix it. Or
maybe it's not the LED current at all.
It is surprising that Tek apparently never fixed it.
Or that they possibly didn't follow one of the cardinal rules in
low-jitter designs: Never, ever, have a load change. Anywhere.

One debug session where I finally found the noise source was a RAM
board, in the days when this stuff was very power-hungry, toasty and
big. They were loading RAM banks ping-pong style but the duty cycle for
each was less than 50%. Meaning there were gaps where the whole circuit
sudenly drew much less current. The fix was to fill that up, I don't
remember whether we stretched the load clock or just let some dummy
process fill the gap but afterwards the noise was gone.
--
Regards, Joerg

http://www.analogconsultants.com/
John Larkin
2012-05-16 00:15:23 UTC
Permalink
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
I'll have to look into that one of these days. Older LEDs used a lot
of current. Maybe a newer LED and a bigger resistor would fix it. Or
maybe it's not the LED current at all.
It is surprising that Tek apparently never fixed it.
Or that they possibly didn't follow one of the cardinal rules in
low-jitter designs: Never, ever, have a load change. Anywhere.
One debug session where I finally found the noise source was a RAM
board, in the days when this stuff was very power-hungry, toasty and
big. They were loading RAM banks ping-pong style but the duty cycle for
each was less than 50%. Meaning there were gaps where the whole circuit
sudenly drew much less current. The fix was to fill that up, I don't
remember whether we stretched the load clock or just let some dummy
process fill the gap but afterwards the noise was gone.
OK, I'll reveal one of my Great Secrets: the key to picosecond-jitter
circuitry is often the low frequency stuff: power supplies, DAC noise,
ground loops, 1/f, thermals.
--
John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Joerg
2012-05-16 00:33:49 UTC
Permalink
Post by John Larkin
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
I'll have to look into that one of these days. Older LEDs used a lot
of current. Maybe a newer LED and a bigger resistor would fix it. Or
maybe it's not the LED current at all.
It is surprising that Tek apparently never fixed it.
Or that they possibly didn't follow one of the cardinal rules in
low-jitter designs: Never, ever, have a load change. Anywhere.
One debug session where I finally found the noise source was a RAM
board, in the days when this stuff was very power-hungry, toasty and
big. They were loading RAM banks ping-pong style but the duty cycle for
each was less than 50%. Meaning there were gaps where the whole circuit
sudenly drew much less current. The fix was to fill that up, I don't
remember whether we stretched the load clock or just let some dummy
process fill the gap but afterwards the noise was gone.
OK, I'll reveal one of my Great Secrets: the key to picosecond-jitter
circuitry is often the low frequency stuff: power supplies, DAC noise,
ground loops, 1/f, thermals.
You forgot two: Beer, and Sutro Tower :-)
--
Regards, Joerg

http://www.analogconsultants.com/
John Larkin
2012-05-16 18:04:26 UTC
Permalink
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
I'll have to look into that one of these days. Older LEDs used a lot
of current. Maybe a newer LED and a bigger resistor would fix it. Or
maybe it's not the LED current at all.
It is surprising that Tek apparently never fixed it.
Or that they possibly didn't follow one of the cardinal rules in
low-jitter designs: Never, ever, have a load change. Anywhere.
One debug session where I finally found the noise source was a RAM
board, in the days when this stuff was very power-hungry, toasty and
big. They were loading RAM banks ping-pong style but the duty cycle for
each was less than 50%. Meaning there were gaps where the whole circuit
sudenly drew much less current. The fix was to fill that up, I don't
remember whether we stretched the load clock or just let some dummy
process fill the gap but afterwards the noise was gone.
OK, I'll reveal one of my Great Secrets: the key to picosecond-jitter
circuitry is often the low frequency stuff: power supplies, DAC noise,
ground loops, 1/f, thermals.
You forgot two: Beer, and Sutro Tower :-)
Beer doesn't cause jitter. Coffee causes jitter.
--
John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Joerg
2012-05-16 18:10:34 UTC
Permalink
Post by John Larkin
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
I'll have to look into that one of these days. Older LEDs used a lot
of current. Maybe a newer LED and a bigger resistor would fix it. Or
maybe it's not the LED current at all.
It is surprising that Tek apparently never fixed it.
Or that they possibly didn't follow one of the cardinal rules in
low-jitter designs: Never, ever, have a load change. Anywhere.
One debug session where I finally found the noise source was a RAM
board, in the days when this stuff was very power-hungry, toasty and
big. They were loading RAM banks ping-pong style but the duty cycle for
each was less than 50%. Meaning there were gaps where the whole circuit
sudenly drew much less current. The fix was to fill that up, I don't
remember whether we stretched the load clock or just let some dummy
process fill the gap but afterwards the noise was gone.
OK, I'll reveal one of my Great Secrets: the key to picosecond-jitter
circuitry is often the low frequency stuff: power supplies, DAC noise,
ground loops, 1/f, thermals.
You forgot two: Beer, and Sutro Tower :-)
Beer doesn't cause jitter.
After the 10th pint it can :-)
Post by John Larkin
Coffee causes jitter.
Depends on the quantity. Once past the point where the jitter stops and
someone has to call an ambulance it may be too late.
--
Regards, Joerg

http://www.analogconsultants.com/
k***@att.bizzzzzzzzzzzz
2012-05-16 20:52:12 UTC
Permalink
On Wed, 16 May 2012 11:04:26 -0700, John Larkin
Post by John Larkin
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
Post by Joerg
Post by John Larkin
On Tue, 15 May 2012 12:41:43 -0400, Phil Hobbs
Post by Phil Hobbs
Post by John Larkin
On Tue, 15 May 2012 11:39:21 -0400, Phil Hobbs
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Usually the pads on small parts are so tiny that pad capacitance is
much less than device capacitance. But of course you can do the math.
Ground cutouts help, especially if ground is layer 2 of a multilayer.
Oh, our EM sims and ground cutouts seem to have worked pretty well on
http://dl.dropbox.com/u/53724080/SED/T240_pulse_1.JPG
That's the 10/90 rise and fall time. For some reason, people in the
fast pulse biz like to use 20/80 rise time in their specs, and
sometimes actually admit it. If I do that, I get...
http://dl.dropbox.com/u/53724080/SED/T240_pulse_2080.JPG
42 picosecond rise and fall! That was done with a 40 GHz sampling
scope and essentially zero cable between the pulser and the sampling
head. Just a few inches of coax trash the risetime at these speeds.
The SMAs have to be carefully torqued, too.
Very pretty. Another factor of 2 and you'd be in SD-24 territory.
BTW I get occasional low-frequency mis-triggering on the rising edge of
TDR pulses in my 11802, so that there's sometimes a lump of junk out ~50
ps in front of the rising edge. Happens on two different SD-24s.
Nothing too serious at the moment, as long as it doesn't deteriorate
rapidly.
I haven't noticed that. I'll look.
You can see a famous SD24 bug: the TDR step time shifts some
picoseconds back and forth in sync with the blinking "TDR" led.
That could possibly be solved by one swift motion with the wire cutters
... snip :-)
I'll have to look into that one of these days. Older LEDs used a lot
of current. Maybe a newer LED and a bigger resistor would fix it. Or
maybe it's not the LED current at all.
It is surprising that Tek apparently never fixed it.
Or that they possibly didn't follow one of the cardinal rules in
low-jitter designs: Never, ever, have a load change. Anywhere.
One debug session where I finally found the noise source was a RAM
board, in the days when this stuff was very power-hungry, toasty and
big. They were loading RAM banks ping-pong style but the duty cycle for
each was less than 50%. Meaning there were gaps where the whole circuit
sudenly drew much less current. The fix was to fill that up, I don't
remember whether we stretched the load clock or just let some dummy
process fill the gap but afterwards the noise was gone.
OK, I'll reveal one of my Great Secrets: the key to picosecond-jitter
circuitry is often the low frequency stuff: power supplies, DAC noise,
ground loops, 1/f, thermals.
You forgot two: Beer, and Sutro Tower :-)
Beer doesn't cause jitter.
It does when you stop. ;-)
Post by John Larkin
Coffee causes jitter.
Sure. Nothing moves without it.
tm
2012-05-15 17:03:44 UTC
Permalink
I am in the process of repairing a Tektronix 11802 that I got on ebay
recently. Most of the issues have been resolved by replacing NVRAM
batteries.

However, I think there might be one EPROM having issues. Would one or more
of you that own the 11802 possibly make binaries from the eproms? If the
Executive and Time base controller have Version 10.xx firmware or greater,
that would really be a plus.

If you have the 11801 and need the firmware => 10.xx, I can help.

The firmware is in a total of 20 27C512 EPROMS so it will take some time to
copy them. These EPROMS dont last forever so having a backup may save you a
future problem.


Regards
unknown
2012-05-15 22:33:47 UTC
Permalink
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Might be a bit hot, but instead of a GND plane you could bootstrap the
parasitics and have a small buffered copper area on layer 2 under the
gate node.
--
Thanks,
Fred.
Phil Hobbs
2012-05-15 22:50:27 UTC
Permalink
Post by unknown
Post by Phil Hobbs
Post by Joerg
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
Post by b***@gmail.com
Post by Phil Hobbs
There are a few people posting to this thread (Fred B, Bill S and Tim
Shoppa) that I can see in Google Groups on my phone but not on
Supernews, which is weird.
Just so you don't think I'm ignoring you guys,
(a) (Bill S)
You can make a triangular wave with just a comparator - the comparator
output pin generates a square wave, but you generate a triangular wave
at the inverting input, and the corners will be as good as the
transition times at the output - about 250psec with the MC100EP116.
Linearity will be controlled by the voltage excursion you allow. You
will be generating an exponential decays rather than linear ramps, but
for a sufficiently small excursion the non-linearity won't be
dramatic.
(Plus another post with an LT1016 circuit)
I really want a nice predictable accurate flat temperature stable high
and low slope on the triangle, so that I get good rectangular pulses at
the output. That puts exponentials and bipolar output stages pretty
well out of court, e.g. the LT1016. Thanks though.
(b) (Tim S)
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
The idea is to make it just like tweaking up a scope probe, for exactly
the reason you give. The circuit problem is how to make that happen.
It really needs to be an asymmetric triangle, because of the unusual
application. This amp is something pretty special--being shot noise
limited at 1 nA in a 100 MHz bandwidth is a pretty good parlour trick,
if you run the numbers. The shot noise limit is SNR (dB) = 10
log(N/(2B)) where N is the number of electrons per second.
A nanoamp in 5 ns is 31 electrons, so the shot noise is about 5-1/2
electrons, which is pretty good going in a built-up circuit. (Easy in a
CCD, but you can't put a wire on a CCD pixel.) So assuming it works as
designed, I ought to have bragging rights for awhile.
The key to doing this is having really low input capacitance, under 1 pF
and preferably more like 0.3 pF, which is very hard to do with packaged
parts. Because the input capacitance is so small, I don't want to add
to it, and therefore the right approach is to generate an accurate
triangle wave and differentiate it with a really really small coupling
capacitance. (The amp is supposed to be current-sensitive anyway.) The
capacitance of an additional pad is much too large.
(c) (Fred B)
If you want really fast edge rates then you're not going to beat
working with a square wave (or rectangular in your case) drive of a
fast buffer with an RC-analog feedback. Your input source could be an
HC Schmitt considering the edge speed-up after the input attenuation,
I need really triangular triangles, for the reasons above. Square waves
are a good deal easier, I agree.
The square wave circuit does the differentiation for you in feedback. C2 and R2 represent your pad capacitance and input resistance. Then by choosing a feedback R1 C1 with identical time constant, the square wave voltages across R2 and R1 will be equal. It's a way of putting the test waveform on your circuit input without tapping it with anything less than ultra-high Z at your frequencies of interest.
So why bother with a parts intensive fussy triangle generator, which is just an approximation anyway, when you can put the end result you want there directly, a rectangular waveform.
Remember that 0.3 pF number. That's about two pads' worth, one for
the pHEMT gate and one for the 100M current feedback resistor. (The
biochip will be wire-bonded to the board.)
I'm not hanging anything else on there, because it degrades
performance linearly with capacitance. And having to match the TCs
manually is what this circuit is designed to calibrate out. Otherwise
it would need another calibrator, which would need another
calibrator, ....
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Your initial post said something about 0.8p input capacitance, now are you saying 0.3p? You're not going to get much of a step across that with the differentiated triangle. And you keep talking about TCs. How harsh is the typical PCR lab anyway? I would think 15o-30o covers it in the extreme.
Do the math. All I need is 10 nA, which I get with 200 kV/s into 0.05
pF coupling capacitance. The 0.3 pF is a wish, 0.8 is what I expect to
get. But even another 0.1 pF is 1 dB of SNR degradation, so since I
need a shield anyway, I'm going to use that.
Looks like you may not want to use FR4 for this. Maybe Rogers 5000 or
Teflon?
--
Regards, Joerg
http://www.analogconsultants.com/
Something with a low epsilon would make sense, for sure. My test board
has a ground plane cutout about 200 mils square under the gate node, but
using something with epsilon = 2.2 instead of 4.6ish would be a win.
Might be a bit hot, but instead of a GND plane you could bootstrap the
parasitics and have a small buffered copper area on layer 2 under the
gate node.
--
Thanks,
Fred.
Bootstrapping doesn't help in this instance--I'm letting the gate node
have whatever TC it wants, and fixing it up afterwards by
differentiating. Trying to do few-electron things in a built-up circuit
requires a certain chastity of outlook. ;)

I need the shield on top anyway, because otherwise this thing is going
to see stray capacitance from passing airplanes.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Bill Sloman
2012-05-11 14:32:59 UTC
Permalink
On May 11, 4:11 pm, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed.  I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode.  Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10.  A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end.  It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output.  This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached.  In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample.  So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily.  The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling.  At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number.  A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant.  (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
The classic way of making a triangular wave is with a comparator

http://www.edn.com/contents/images/101603di.pdf

and the Linear Technology LT1016 is both fast and well-behaved.

The ON Semiconductors MC100EP116

http://www.onsemi.com/pub_link/Collateral/MC10EP116-D.PDF

is probably cheaper and faster. The gain per stage isn't all that
high, but you can string a few together - you get six in a package.

John Larkin has recommended them from time to time, though he'll
probably come up with something faster today.

--
Bill Sloman, Nijmegen
George Herold
2012-05-11 15:51:36 UTC
Permalink
On May 11, 10:11 am, Phil Hobbs
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed.  I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode.  Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10.  A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end.  It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output.  This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached.  In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample.  So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily.  The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling.  At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number.  A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant.  (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot nethttp://electrooptical.net
If I understand you correctly, you want a very linear ramp. Keeping
it symmetric is not important; in fact you are making it asymmetric on
purpose. And it’s really the user tweak that is critical. (I assume
for the in house tweaks they can throw money at it, buy some good Arb.
func generator, maybe.) And after the ramp ‘gets going’ a little non-
linearly (a few percent) is not going to be a big deal. It’s that
first few nano seconds of the ramp that are critical.

Just seeing if I understand your problem.

I don’t have any wisdom though :^( Sorry.

George H.
b***@gmail.com
2012-05-13 01:06:18 UTC
Permalink
Post by Phil Hobbs
Hi all,
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
will.
If you want really fast edge rates then you're not going to beat working with a square wave (or rectangular in your case) drive of a fast buffer with an RC-analog feedback. Your input source could be an HC Schmitt considering the edge speed-up after the input attenuation, should be easy to get sub-nanosecond edge rates:
Please view in a fixed-width font such as Courier.

.
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.
. _
. /|
. .--||---.
. | / |
. | |
. | | |\
. >---+-[19R]-+----------|+\ C2 _ _
. | | > ---+--||---, _| |_| |_
. _ _ | .--|-/ | |
. _| |_| |_ [R] | |/ C1 | |
. | | --- [R2]
. | | --- |
. --- | | |
. | | ---
. | |
. '----------+
. |
. |
. [R1]
. |
. R1C1=R2C2 |
. ---
.
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.
Post by Phil Hobbs
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
generator.
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
Bill Sloman
2012-05-13 11:10:28 UTC
Permalink
On May 11, 4:11 pm, Phil Hobbs
<***@electrooptical.net> wrote:

<snip>

Try this. The triangular wave appears at the inverting input to the
LT1016 (labelled "out" i=on the schematic).

Version 4
SHEET 1 4648 1292
WIRE -224 -64 -384 -64
WIRE -16 -64 -224 -64
WIRE 208 -64 -16 -64
WIRE 352 -64 208 -64
WIRE 960 -64 352 -64
WIRE 1376 -64 960 -64
WIRE 1472 -64 1376 -64
WIRE -16 -32 -16 -64
WIRE 208 -32 208 -64
WIRE -224 16 -224 -64
WIRE 1376 48 1376 -64
WIRE -16 80 -16 48
WIRE 1136 80 -16 80
WIRE -384 128 -384 -64
WIRE 352 128 352 -64
WIRE -16 160 -16 80
WIRE 48 160 -16 160
WIRE 320 160 48 160
WIRE 576 160 400 160
WIRE 1376 160 1376 128
WIRE 1520 160 1376 160
WIRE 208 192 208 48
WIRE 320 192 208 192
WIRE 960 208 960 -64
WIRE 1136 208 1136 80
WIRE -16 224 -16 160
WIRE 1520 240 1520 160
WIRE 208 256 208 192
WIRE 480 256 208 256
WIRE 576 256 576 160
WIRE 576 256 560 256
WIRE 720 256 576 256
WIRE 896 256 800 256
WIRE 1248 256 1200 256
WIRE 1376 256 1376 160
WIRE 1376 256 1328 256
WIRE 1376 272 1376 256
WIRE 208 288 208 256
WIRE 1040 304 960 304
WIRE 1136 304 1040 304
WIRE -384 400 -384 208
WIRE -304 400 -384 400
WIRE -224 400 -224 80
WIRE -224 400 -304 400
WIRE -192 400 -224 400
WIRE -16 400 -16 288
WIRE -16 400 -192 400
WIRE 208 400 208 368
WIRE 208 400 -16 400
WIRE 352 400 352 224
WIRE 352 400 208 400
WIRE 368 400 368 224
WIRE 368 400 352 400
WIRE 1376 400 1376 352
WIRE 1376 400 368 400
WIRE 1520 400 1520 304
WIRE 1520 400 1376 400
WIRE -304 448 -304 400
WIRE 1040 448 1040 304
WIRE -384 512 -384 400
WIRE -192 512 -192 400
WIRE -384 704 -384 592
WIRE -192 704 -192 576
WIRE -192 704 -384 704
WIRE 336 704 336 224
WIRE 336 704 -192 704
WIRE 1040 704 1040 528
WIRE 1040 704 336 704
WIRE 1344 704 1040 704
FLAG -304 448 0
FLAG 48 160 out
SYMBOL Comparators\\LT1016 352 112 R0
SYMATTR InstName U1
SYMBOL voltage -384 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap -32 224 R0
SYMATTR InstName C1
SYMATTR Value 4.7n
SYMBOL res -32 -48 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL voltage -384 496 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 192 -48 R0
SYMATTR InstName R3
SYMATTR Value 3.3k
SYMBOL res 192 272 R0
SYMATTR InstName R4
SYMATTR Value 2.2k
SYMBOL res 576 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 3.3k
SYMBOL cap -240 16 R0
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL cap -208 512 R0
SYMATTR InstName C3
SYMATTR Value 100n
SYMBOL npn 896 208 R0
SYMATTR InstName Q1
SYMATTR Value BFR92A
SYMBOL npn 1200 208 M0
SYMATTR InstName Q2
SYMATTR Value BFR92A
SYMBOL res 1024 432 R0
SYMATTR InstName R2
SYMATTR Value 7.5k
SYMBOL res 1344 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 33
SYMBOL res 816 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 33
SYMBOL res 1360 32 R0
SYMATTR InstName R8
SYMATTR Value 3.6k
SYMBOL res 1360 256 R0
SYMATTR InstName R9
SYMATTR Value 1.3k
SYMBOL cap 1504 240 R0
SYMATTR InstName C4
SYMATTR Value 100n
TEXT -16 504 Left 2 !.tran 0 1m 1u startup
TEXT 1272 504 Left 2 !.model BFR92A NPN(IS=0.1213E-15 VAF=30 BF=94.73
IKF=0.46227 XTB=0 BR=10.729 CJC=946.47E-15 CJE=10.416E-15
TR=1.2744E-9 TF=26.796E-12 ITF=0.0044601 VTF=0.32861 XTF=0.3817
RB=14.998 RC=0.13793 RE=0.29088 Vceo=15 Icrating=4m mfg=Infineon)

--
Bill Sloman, Nijmegen
Tim Shoppa
2012-05-13 13:31:17 UTC
Permalink
On May 11, 10:11 am, Phil Hobbs
Post by Phil Hobbs
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily.  The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
[...]
Post by Phil Hobbs
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant.  (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?

Tim.
Jasen Betts
2012-05-15 09:28:17 UTC
Permalink
Post by George Herold
On May 11, 10:11 am, Phil Hobbs
Post by Phil Hobbs
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily.  The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
[...]
Post by Phil Hobbs
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant.  (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Any wisdom?
I know you have your heart set on a triangle wave.... but scope and
scope probes have allowed users to tweak probe padding compensation
with square waves for a long time. This is a tweak that un-EE-
sophisticated users do all the time as part of many procedures. Same
problem? Or different?
as I unsersand it he wants to feed the triangle wave through a
capacitor into a resistor to generate the calibration vaveform
--
⚂⚃ 100% natural

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