2012-05-11 14:11:49 UTC
So I have this nice 1 nA/100 MHz shot noise limited front end mostly
designed. I can't post the schematic due to NDA issues, but the basic
idea is to use an Avago ATF38143 pHEMT running common-source, with a
BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early
voltage of the BFP640F, the front end runs at a DC gain of about 32, and
goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series
with its base keeps the BJT from singing at 6 GHz, which it otherwise
There's a current feedback loop that uses a 100 meg feedback resistor to
stabilize the operating current of the front end. It rolls off at
around 10 kHz.
A current pulse at the input causes the ~0.8 pF input capacitance to
charge up, which produces a ramp at the first stage output. This gets
differentiated by a parallel RC to produce a nice pulse output again.
100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably
realistic board strays included.
The bad news is that the time constants have to be right, which means
they have to be tweaked.
The high frequency gain is proportional to 1/C_in, so the low frequency
gain has to be tweaked to match, once the sample is attached. In
addition, the bias and differentiator TCs have to match, though those
don't have to be tweaked for each sample. So it needs two production
tweaks and one user tweak, about like a scope probe.
To save wear and tear on the users, I want to put in a good
self-calibration signal so that they can tweak it easily. The three
tweaks all have quite different TCs, so it isn't hard to get right--just
go in order from slowest to fastest, then repeat, and you're done.
However, since the input is 0.8 pF // 100 meg, I can't connect anything
to it to do the calibration, which is a problem.
I'm planning to use an asymmetrical ramp generator connected to a pad
near the input node, so that I get about 0.05 pF of coupling. At that
point, a ramp of 0.2 V/us will give me 10 nA of input current, which is
a convenient number. A volt peak to peak is fine.
However, I really want the pulse tops flat and the edges square (ideally
1 ns or faster) so that we can really test the full performance of the
gizmo--in other words, I need a really triangular triangle wave
The good news is that it doesn't have to drive anything much--just its
own output trace--and that the ramp is pretty slow, so I can use a big
high voltage NPO integration cap to swamp out the nonlinear capacitances
of the active devices--1 mA into 4700 pF @ 100V, or something like that.
The bad news is that I don't get to wring this board out myself, so it
also has to be reasonably idiot-resistant. (My customers are very smart
people, but they aren't circuits folks, and I don't know what their
in-house EE support looks like.)
Dr Philip C D Hobbs
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net